### Equations

********** Mapped Logic **********
$OpTx$FX_DC$461 <= ((NOT floppy_mode(2) AND NOT adr(13)) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)));
$OpTx$FX_DC$475 <= ((NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)));
$OpTx$FX_DC$492 <= ((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1)) OR (NOT adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1)));
$OpTx$FX_DC$501 <= (ram_ce AND rom_ce);
$OpTx$FX_DC$502 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(10) AND adr(11)));
$OpTx$FX_DC$515 <= (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(7) AND NOT adr(10));
$OpTx$FX_DC$517 <= ((NOT rom_source_is_ram AND NOT $OpTx$FX_DC$556 AND NOT $OpTx$FX_DC$502) OR (NOT $OpTx$FX_DC$556 AND NOT $OpTx$FX_DC$502 AND N64/N64_D2));
$OpTx$FX_DC$529 <= (adr(4) AND adr(3) AND adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475);
$OpTx$FX_DC$531 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(1) AND NOT adr(7) AND NOT adr(10)));
$OpTx$FX_DC$554 <= ((NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(10) AND adr(11)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(7) AND NOT adr(10)) OR (floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(11)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND $OpTx$FX_DC$475));
$OpTx$FX_DC$556 <= ((N104/N104_D2) OR ($OpTx$FX_DC$515) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(11)) OR (floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15)));
$OpTx$FX_SC$508 <= (NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2);
$OpTx$FX_SC$520 <= ((NOT adr(12) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND reset AND $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND reset));
N104/N104_D2 <= (NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2);
N11/N11_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)) OR (NOT adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)));
N2/N2_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15)) OR (adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)) OR (adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)));
N27/N27_D2 <= ((NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)));
N64/N64_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND $OpTx$FX_DC$475));
FDCPE_centronics_clk: FDCPE port map (centronics_clk,centronics_clk_D,NOT phi2,'0','0'); centronics_clk_D <= ((centronics_clk AND NOT turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (NOT reset AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (d7_ram_rom.PIN AND data(4).PIN AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2));
FDCPE_centronics_data: FDCPE port map (centronics_data,centronics_data_D,NOT phi2,'0','0'); centronics_data_D <= ((centronics_data AND NOT turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (NOT reset AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (d7_ram_rom.PIN AND data(5).PIN AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2));
FDCPE_centronics_strobe: FDCPE port map (centronics_strobe,centronics_strobe_D,NOT phi2,'0','0'); centronics_strobe_D <= ((NOT centronics_strobe AND NOT turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2) OR (NOT data(6).PIN AND d7_ram_rom.PIN AND reset AND turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2));
FDCPE_cfg_led: FDCPE port map (cfg_led,cfg_led_D,NOT phi2,'0','0'); cfg_led_D <= ((data(0).PIN AND reset AND $OpTx$FX_DC$529) OR (cfg_led AND reset AND NOT $OpTx$FX_DC$529));
check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 <= (NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1));
check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 <= ((NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND NOT adr(15)) OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND NOT adr(14) AND NOT adr(15)) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(13) AND NOT adr(14) AND NOT adr(15)));
d7_ram_rom_I <= data(7).PIN; d7_ram_rom <= d7_ram_rom_I when d7_ram_rom_OE = '1' else 'Z'; d7_ram_rom_OE <= (phi2 AND NOT rw AND NOT $OpTx$FX_DC$501);
data_I(0) <= ((cfg_enc_a AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_0 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (floppy_mode(0) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (rom_base_bank_0 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(0) <= data_I(0) when data_OE(0) = '1' else 'Z'; data_OE(0) <= data_0_or0000/data_0_or0000_D2;
data_I(1) <= ((cfg_enc_b AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_1 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (floppy_mode(1) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (rom_base_bank_1 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(1) <= data_I(1) when data_OE(1) = '1' else 'Z'; data_OE(1) <= data_0_or0000/data_0_or0000_D2;
data_I(2) <= ((floppy_mode(2) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_enc_ok AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND rom_bank_c000_2 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_3 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(2) <= data_I(2) when data_OE(2) = '1' else 'Z'; data_OE(2) <= data_0_or0000/data_0_or0000_D2;
data_I(3) <= ((floppy_mode(3) AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_sw1 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND rom_bank_c000_3 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_4 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_3 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(3) <= data_I(3) when data_OE(3) = '1' else 'Z'; data_OE(3) <= data_0_or0000/data_0_or0000_D2;
data_I(4) <= ((cfg_sw2 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND rom_bank_c000_4 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_5 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_4 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(4) <= data_I(4) when data_OE(4) = '1' else 'Z'; data_OE(4) <= data_0_or0000/data_0_or0000_D2;
data_I(5) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_5 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_6 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_5 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(5) <= data_I(5) when data_OE(5) = '1' else 'Z'; data_OE(5) <= data_0_or0000/data_0_or0000_D2;
data_I(6) <= (rom_base_bank_6 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2); data(6) <= data_I(6) when data_OE(6) = '1' else 'Z'; data_OE(6) <= data_0_or0000/data_0_or0000_D2;
data_I(7) <= NOT (((EXP14_.EXP) OR (NOT i2c_data_pin.PIN AND $OpTx$FX_DC$475 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (adr(12) AND rw AND NOT adr(11) AND NOT centronics_busy AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (rom_bank_c000_enable(0) AND $OpTx$FX_DC$475 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT d7_ram_rom.PIN AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT rom_source_is_ram AND $OpTx$FX_DC$475 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT adr(12) AND NOT d7_ram_rom.PIN AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT rw AND NOT d7_ram_rom.PIN AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT d7_ram_rom.PIN AND adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT d7_ram_rom.PIN AND NOT $OpTx$FX_DC$475 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2))); data(7) <= data_I(7) when data_OE(7) = '1' else 'Z'; data_OE(7) <= data_7_or0005/data_7_or0005_D2;
data_0_cmp_eq0000/data_0_cmp_eq0000_D2 <= (adr(4) AND adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8));
data_0_cmp_eq0001/data_0_cmp_eq0001_D2 <= (NOT adr(4) AND NOT adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8));
data_0_cmp_eq0002/data_0_cmp_eq0002_D2 <= (adr(4) AND NOT adr(3) AND NOT adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8));
data_0_or0000/data_0_or0000_D2 <= ((phi2 AND rw AND $OpTx$FX_DC$475 AND NOT $OpTx$FX_SC$508) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND phi2 AND adr(13) AND adr(14) AND rw AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475));
data_7_or0005/data_7_or0005_D2 <= ((phi2 AND rw AND NOT $OpTx$FX_DC$501) OR (adr(12) AND phi2 AND rw AND NOT adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (phi2 AND rw AND $OpTx$FX_DC$475 AND NOT $OpTx$FX_SC$508 AND NOT check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2) OR (NOT adr(4) AND NOT adr(3) AND adr(12) AND phi2 AND adr(13) AND adr(14) AND rw AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND adr(5) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND phi2 AND adr(13) AND adr(14) AND rw AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475));
FDCPE_density0: FDCPE port map (density(0),density_D(0),NOT phi2,'0','0'); density_D(0) <= ((NOT reset) OR (density(0) AND NOT $OpTx$FX_DC$492) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(6).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(7).PIN));
FDCPE_density1: FDCPE port map (density(1),density_D(1),NOT phi2,'0','0'); density_D(1) <= ((NOT reset) OR (density(1) AND NOT $OpTx$FX_DC$492) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(7).PIN));
FDCPE_density2: FDCPE port map (density(2),density_D(2),NOT phi2,'0','0'); density_D(2) <= ((NOT reset) OR (density(2) AND NOT $OpTx$FX_DC$492) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(2).PIN AND adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(6).PIN));
fdc_write_out <= ((archiver_a11 AND fdc_write_in) OR (fdc_write_in AND NOT riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST));
FDCPE_floppy_mode0: FDCPE port map (floppy_mode(0),floppy_mode_D(0),NOT phi2,'0','0'); floppy_mode_D(0) <= ((floppy_mode(0) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(0).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2));
FDCPE_floppy_mode1: FDCPE port map (floppy_mode(1),floppy_mode_D(1),NOT phi2,'0','0'); floppy_mode_D(1) <= ((floppy_mode(1) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(1).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2));
FDCPE_floppy_mode2: FDCPE port map (floppy_mode(2),floppy_mode_D(2),NOT phi2,'0','0'); floppy_mode_D(2) <= ((floppy_mode(2) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(2).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2));
FDCPE_floppy_mode3: FDCPE port map (floppy_mode(3),floppy_mode_D(3),NOT phi2,'0','0'); floppy_mode_D(3) <= ((floppy_mode(3) AND NOT floppy_mode_0__or0000/floppy_mode_0__or0000_D2) OR (data(3).PIN AND reset AND floppy_mode_0__or0000/floppy_mode_0__or0000_D2));
floppy_mode_0__or0000/floppy_mode_0__or0000_D2 <= ((NOT reset) OR (adr(4) AND NOT adr(3) AND adr(0) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8) AND $OpTx$FX_DC$475));
FTCPE_happy_a12: FTCPE port map (happy_a12,happy_a12_T,NOT phi2,'0','0'); happy_a12_T <= ((NOT happy_a12 AND NOT reset AND happy_a12__or0001/happy_a12__or0001_D2) OR (adr(3) AND adr(0) AND NOT happy_a12 AND NOT adr(1) AND NOT adr(2) AND happy_a12__or0001/happy_a12__or0001_D2) OR (adr(3) AND NOT adr(0) AND happy_a12 AND NOT adr(1) AND NOT adr(2) AND reset AND happy_a12__or0001/happy_a12__or0001_D2));
happy_a12__or0001/happy_a12__or0001_D2 <= ((NOT reset) OR (adr(4) AND NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND adr(15) AND adr(9) AND adr(7) AND adr(10) AND adr(5) AND adr(11) AND adr(6) AND adr(8)));
FTCPE_i2c_clk: FTCPE port map (i2c_clk,i2c_clk_T,NOT phi2,'0','0'); i2c_clk_T <= ((NOT i2c_clk AND NOT reset) OR (adr(0) AND NOT rw AND NOT i2c_clk AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT adr(0) AND NOT rw AND i2c_clk AND reset AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2));
i2c_clk_and0000/i2c_clk_and0000_D2 <= (NOT adr(4) AND NOT adr(3) AND adr(12) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(9) AND NOT adr(7) AND NOT adr(10) AND adr(5) AND NOT adr(2) AND NOT adr(11) AND NOT adr(6) AND NOT adr(8));
i2c_clk_pin_I <= '0'; i2c_clk_pin <= i2c_clk_pin_I when i2c_clk_pin_OE = '1' else 'Z'; i2c_clk_pin_OE <= NOT i2c_clk;
FTCPE_i2c_data: FTCPE port map (i2c_data,i2c_data_T,NOT phi2,'0','0'); i2c_data_T <= ((NOT i2c_data AND NOT reset) OR (NOT rw AND NOT i2c_data AND adr(1) AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT rw AND i2c_data AND NOT adr(1) AND reset AND $OpTx$FX_DC$475 AND i2c_clk_and0000/i2c_clk_and0000_D2));
i2c_data_pin_I <= '0'; i2c_data_pin <= i2c_data_pin_I when i2c_data_pin_OE = '1' else 'Z'; i2c_data_pin_OE <= NOT i2c_data;
io_1050 <= NOT (((NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(10)) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(7) AND NOT adr(11)) OR (adr(9) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (adr(7) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (adr(10) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(7)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(10))));
FDCPE_ram_bank_0: FDCPE port map (ram_bank_0,ram_bank_0_D,NOT phi2,'0','0'); ram_bank_0_D <= ((data(0).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_0 AND NOT N27/N27_D2));
FDCPE_ram_bank_1: FDCPE port map (ram_bank_1,ram_bank_1_D,NOT phi2,'0','0'); ram_bank_1_D <= ((data(1).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_1 AND NOT N27/N27_D2));
FDCPE_ram_bank_2: FDCPE port map (ram_bank_2,ram_bank_2_D,NOT phi2,'0','0'); ram_bank_2_D <= ((data(2).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_2 AND NOT N27/N27_D2));
FDCPE_ram_bank_3: FDCPE port map (ram_bank_3,ram_bank_3_D,NOT phi2,'0','0'); ram_bank_3_D <= ((data(3).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_3 AND NOT N27/N27_D2));
FDCPE_ram_bank_4: FDCPE port map (ram_bank_4,ram_bank_4_D,NOT phi2,'0','0'); ram_bank_4_D <= ((data(4).PIN AND $OpTx$FX_SC$520) OR (reset AND ram_bank_4 AND NOT N27/N27_D2));
FDCPE_ram_bank_5: FDCPE port map (ram_bank_5,ram_bank_5_D,NOT phi2,'0','0'); ram_bank_5_D <= ((reset AND ram_bank_5 AND NOT N27/N27_D2) OR (NOT adr(12) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND reset AND $OpTx$FX_DC$475));
ram_ce <= NOT ((($OpTx$FX_DC$556) OR ($OpTx$FX_DC$502) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND rom_source_is_ram AND rw) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15) AND NOT ram_bank_4) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rom_bank_c000_enable(0) AND rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND rw) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND rw) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15) AND NOT ram_bank_3)));
ram_rom_adr(8) <= ((adr(9) AND NOT N104/N104_D2 AND $OpTx$FX_DC$515) OR (adr(8) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515));
ram_rom_adr(9) <= NOT ((NOT adr(9) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515));
ram_rom_adr(10) <= ((N104/N104_D2) OR (adr(10)) OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT adr(7)));
ram_rom_adr(11) <= NOT (((adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT turbo_rom_adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT archiver_a11 AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(10) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT adr(12) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (floppy_mode(3) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT floppy_mode(0) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (NOT floppy_mode(2) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515) OR (floppy_mode(1) AND NOT adr(11) AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$515)));
ram_rom_adr(12) <= ((EXP23_.EXP) OR (NOT adr(12) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(3) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0 AND NOT adr(11)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(13) AND rom_base_bank_0) OR (floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_0) OR (N104/N104_D2) OR ($OpTx$FX_DC$515) OR (happy_a12.EXP) OR (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2)) OR (floppy_mode(3) AND floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (NOT floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(3) AND floppy_mode(0) AND NOT rom_source_is_ram AND adr(10) AND rom_base_bank_0) OR (adr(12) AND floppy_mode(3) AND NOT rom_source_is_ram AND rw AND rom_base_bank_0 AND adr(11)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(14) AND NOT adr(15) AND rom_base_bank_0) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(14) AND adr(15) AND rom_base_bank_0));
ram_rom_adr(13) <= ((adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rw AND NOT N104/N104_D2) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(11) AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(14) AND adr(15) AND rom_bank_c000_0 AND $OpTx$FX_DC$475 AND NOT N104/N104_D2) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15) AND NOT N104/N104_D2) OR (NOT N104/N104_D2 AND $OpTx$FX_DC$502) OR (NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$531) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND NOT adr(15) AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_0 AND NOT N104/N104_D2));
ram_rom_adr(14) <= (($OpTx$FX_DC$556) OR ($OpTx$FX_DC$502) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(15) AND $OpTx$FX_DC$475) OR (NOT rom_source_is_ram AND adr(14) AND rom_base_bank_2 AND NOT $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND rom_bank_c000_1 AND $OpTx$FX_DC$475) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_1) OR (floppy_mode(3) AND NOT rom_source_is_ram AND rom_base_bank_2) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_2) OR (NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_2));
ram_rom_adr(15) <= ((rom_source_is_ram AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$554) OR (rom_base_bank_3 AND NOT N104/N104_D2 AND NOT $OpTx$FX_DC$554) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND NOT adr(14) AND adr(15) AND ram_bank_2 AND NOT N104/N104_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15) AND rom_bank_c000_2 AND $OpTx$FX_DC$475 AND NOT N104/N104_D2));
ram_rom_adr(16) <= ((NOT $OpTx$FX_DC$517) OR (rom_base_bank_4 AND NOT N64/N64_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_3) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_3 AND $OpTx$FX_DC$475));
ram_rom_adr(17) <= ((NOT $OpTx$FX_DC$517) OR (rom_base_bank_5 AND NOT N64/N64_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_4) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_4 AND $OpTx$FX_DC$475));
ram_rom_adr(18) <= ((NOT $OpTx$FX_DC$517) OR (rom_base_bank_6 AND NOT N64/N64_D2) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_5) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(14) AND adr(15) AND ram_bank_5) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_5 AND $OpTx$FX_DC$475));
ram_rom_oe <= NOT ((phi2 AND rw));
ram_rom_we <= NOT ((phi2 AND NOT rw));
FDCPE_reset: FDCPE port map (reset,reset_sync,NOT phi2,'0','0');
FDCPE_reset_sync: FDCPE port map (reset_sync,reset_in,NOT phi2,'0','0');
riot_ready_in_IBUF$BUF0/riot_ready_in_IBUF$BUF0_TRST <= (floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1));
riot_ready_inout_I <= riot_ready_in; riot_ready_inout <= riot_ready_inout_I when riot_ready_inout_OE = '1' else 'Z'; riot_ready_inout_OE <= NOT ((floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1)));
FDCPE_rom_bank_c000_0: FDCPE port map (rom_bank_c000_0,rom_bank_c000_0_D,NOT phi2,'0','0'); rom_bank_c000_0_D <= ((rom_bank_c000_0 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(0).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 <= ((NOT reset) OR (NOT rw AND $OpTx$FX_DC$475 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2));
FDCPE_rom_bank_c000_1: FDCPE port map (rom_bank_c000_1,rom_bank_c000_1_D,NOT phi2,'0','0'); rom_bank_c000_1_D <= ((NOT rom_bank_c000_1 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (NOT data(1).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
FDCPE_rom_bank_c000_2: FDCPE port map (rom_bank_c000_2,rom_bank_c000_2_D,NOT phi2,'0','0'); rom_bank_c000_2_D <= ((rom_bank_c000_2 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(2).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
FDCPE_rom_bank_c000_3: FDCPE port map (rom_bank_c000_3,rom_bank_c000_3_D,NOT phi2,'0','0'); rom_bank_c000_3_D <= ((rom_bank_c000_3 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(3).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
FDCPE_rom_bank_c000_4: FDCPE port map (rom_bank_c000_4,rom_bank_c000_4_D,NOT phi2,'0','0'); rom_bank_c000_4_D <= ((rom_bank_c000_4 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (reset AND data(4).PIN AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
FDCPE_rom_bank_c000_5: FDCPE port map (rom_bank_c000_5,rom_bank_c000_5_D,NOT phi2,'0','0'); rom_bank_c000_5_D <= ((rom_bank_c000_5 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(5).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
FDCPE_rom_bank_c000_enable0: FDCPE port map (rom_bank_c000_enable(0),rom_bank_c000_enable_D(0),NOT phi2,'0','0'); rom_bank_c000_enable_D(0) <= ((rom_bank_c000_enable(0) AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (NOT data(7).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));
FDCPE_rom_base_bank_0: FDCPE port map (rom_base_bank_0,rom_base_bank_0_D,NOT phi2,'0','0'); rom_base_bank_0_D <= ((rom_base_bank_0 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(0).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 <= ((NOT reset) OR ($OpTx$FX_DC$475 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2));
FDCPE_rom_base_bank_1: FDCPE port map (rom_base_bank_1,rom_base_bank_1_D,NOT phi2,'0','0'); rom_base_bank_1_D <= ((rom_base_bank_1 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(1).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
FDCPE_rom_base_bank_2: FDCPE port map (rom_base_bank_2,rom_base_bank_2_D,NOT phi2,'0','0'); rom_base_bank_2_D <= ((rom_base_bank_2 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(2).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
FDCPE_rom_base_bank_3: FDCPE port map (rom_base_bank_3,rom_base_bank_3_D,NOT phi2,'0','0'); rom_base_bank_3_D <= ((NOT rom_base_bank_3 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(3).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
FDCPE_rom_base_bank_4: FDCPE port map (rom_base_bank_4,rom_base_bank_4_D,NOT phi2,'0','0'); rom_base_bank_4_D <= ((NOT rom_base_bank_4 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (reset AND NOT data(4).PIN AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
FDCPE_rom_base_bank_5: FDCPE port map (rom_base_bank_5,rom_base_bank_5_D,NOT phi2,'0','0'); rom_base_bank_5_D <= ((NOT rom_base_bank_5 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(5).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
FDCPE_rom_base_bank_6: FDCPE port map (rom_base_bank_6,rom_base_bank_6_D,NOT phi2,'0','0'); rom_base_bank_6_D <= ((NOT rom_base_bank_6 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(6).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
rom_ce <= NOT (((NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND floppy_mode(1) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15)) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT rom_source_is_ram AND rw) OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (adr(12) AND floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw) OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(11))));
FDCPE_rom_source_is_ram: FDCPE port map (rom_source_is_ram,rom_source_is_ram_D,NOT phi2,'0','0'); rom_source_is_ram_D <= ((rom_source_is_ram AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(7).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));
FTCPE_summer: FTCPE port map (summer,summer_T,NOT phi2,'0','0'); summer_T <= ((adr(0) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset) OR (adr(0) AND NOT floppy_mode(3) AND floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset));
FDCPE_track_hi0: FDCPE port map (track_hi(0),track_hi_D(0),NOT phi2,'0','0'); track_hi_D(0) <= ((NOT reset) OR (track_hi(0) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND data(4).PIN));
FDCPE_track_hi1: FDCPE port map (track_hi(1),track_hi_D(1),NOT phi2,'0','0'); track_hi_D(1) <= ((NOT reset) OR (track_hi(1) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT adr(1) AND $OpTx$FX_DC$461));
FDCPE_track_hi2: FDCPE port map (track_hi(2),track_hi_D(2),NOT phi2,'0','0'); track_hi_D(2) <= ((NOT reset) OR (track_hi(2) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(2).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND NOT data(4).PIN));
FDCPE_track_hi3: FDCPE port map (track_hi(3),track_hi_D(3),NOT phi2,'0','0'); track_hi_D(3) <= ((NOT reset) OR (track_hi(3) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND data(4).PIN));
FDCPE_track_hi4: FDCPE port map (track_hi(4),track_hi_D(4),NOT phi2,'0','0'); track_hi_D(4) <= ((NOT reset) OR (track_hi(4) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN));
FDCPE_track_hi5: FDCPE port map (track_hi(5),track_hi_D(5),NOT phi2,'0','0'); track_hi_D(5) <= ((NOT reset) OR (track_hi(5) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN));
FDCPE_track_hi6: FDCPE port map (track_hi(6),track_hi_D(6),NOT phi2,'0','0'); track_hi_D(6) <= ((NOT reset) OR (track_hi(6) AND NOT N2/N2_D2) OR (adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN));
FDCPE_track_lo0: FDCPE port map (track_lo(0),track_lo_D(0),NOT phi2,'0','0'); track_lo_D(0) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (track_lo(0) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND data(0).PIN));
FDCPE_track_lo1: FDCPE port map (track_lo(1),track_lo_D(1),NOT phi2,'0','0'); track_lo_D(1) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND data(0).PIN) OR (track_lo(1) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(2).PIN AND NOT data(0).PIN));
FDCPE_track_lo2: FDCPE port map (track_lo(2),track_lo_D(2),NOT phi2,'0','0'); track_lo_D(2) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN) OR (track_lo(2) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(2).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND data(2).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN));
FDCPE_track_lo3: FDCPE port map (track_lo(3),track_lo_D(3),NOT phi2,'0','0'); track_lo_D(3) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN) OR (track_lo(3) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT adr(1) AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN));
FDCPE_track_lo4: FDCPE port map (track_lo(4),track_lo_D(4),NOT phi2,'0','0'); track_lo_D(4) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(2).PIN AND data(0).PIN) OR (track_lo(4) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN));
FDCPE_track_lo5: FDCPE port map (track_lo(5),track_lo_D(5),NOT phi2,'0','0'); track_lo_D(5) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND data(0).PIN) OR (track_lo(5) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND data(0).PIN));
FDCPE_track_lo6: FDCPE port map (track_lo(6),track_lo_D(6),NOT phi2,'0','0'); track_lo_D(6) <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (track_lo(6) AND NOT N11/N11_D2) OR (NOT adr(0) AND NOT floppy_mode(3) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$461) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(2) AND floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND data(0).PIN));
turbo_centronics_clk__or0001/turbo_centronics_clk__or0001_D2 <= ((NOT reset) OR (adr(12) AND NOT adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2));
FDCPE_turbo_rom_adr11: FDCPE port map (turbo_rom_adr(11),turbo_rom_adr_D(11),NOT phi2,'0','0'); turbo_rom_adr_D(11) <= ((NOT turbo_rom_adr(11) AND NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2) OR (NOT data(6).PIN AND reset AND NOT data(4).PIN AND turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2));
FDCPE_turbo_rom_adr12: FDCPE port map (turbo_rom_adr(12),turbo_rom_adr_D(12),NOT phi2,'0','0'); turbo_rom_adr_D(12) <= ((NOT turbo_rom_adr(12) AND NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2) OR (data(5).PIN AND reset AND turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2));
turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 <= ((NOT reset) OR (adr(12) AND NOT d7_ram_rom.PIN AND NOT adr(11) AND check_1050_6810_access_cmp_eq0000/check_1050_6810_access_cmp_eq0000_D2));
turbo_speed_out <= ((floppy_mode(3) AND NOT floppy_mode(0) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT riot_ready_inout.PIN) OR (NOT floppy_mode(3) AND floppy_mode(0) AND floppy_mode(2) AND NOT floppy_mode(1) AND turbo_speed_in));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);