    cpldfit:  version P.20131013                        Xilinx Inc.
                                      Fitter Report
    Design Name: MegaSpeedy                          Date: 11-23-2014,  1:53PM
    Device Used: XC95144XL-10-TQ100
    Fitting Status: Successful

    *************************  Mapped Resource Summary  **************************

    Macrocells     Product Terms    Function Block   Registers      Pins
    Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot
    131/144 ( 91%) 478 /720  ( 66%) 348/432 ( 81%)   56 /144 ( 39%) 81 /81  (100%)

    ** Function Block Resources **

    Function    Mcells      FB Inps     Pterms      IO
    Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
    FB1          16/18       53/54       88/90      11/11*
    FB2          15/18       50/54       81/90      10/10*
    FB3          14/18       43/54       81/90      10/10*
    FB4          14/18       47/54       70/90      10/10*
    FB5          18/18*      46/54       61/90      10/10*
    FB6          18/18*      34/54       26/90      10/10*
    FB7          18/18*      39/54       34/90      10/10*
    FB8          18/18*      36/54       37/90      10/10*
                 -----       -----       -----      -----
                131/144     348/432     478/720     81/81

    * - Resource is exhausted

    ** Global Control Resources **

    Signal 'phi2' mapped onto global clock net GCK3.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    ** Pin Resources **

    Signal Type    Required     Mapped  |  Pin Type            Used    Total
    ------------------------------------|------------------------------------
    Input         :   28          28    |  I/O              :    73      73
    Output        :   41          41    |  GCK/IO           :     3       3
    Bidirectional :   11          11    |  GTS/IO           :     4       4
    GCK           :    1           1    |  GSR/IO           :     1       1
    GTS           :    0           0    |
    GSR           :    0           0    |
                     ----        ----
            Total     81          81

    ** Power Data **

    There are 0 macrocells in high performance mode (MCHP).
    There are 131 macrocells in low power mode (MCLP).
    End of Mapped Resource Summary
    **************************  Errors and Warnings  ***************************

    WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
       use the default filename of 'MegaSpeedy.ise'.
    INFO:Cpld - Inferring BUFG constraint for signal 'data<7>' based upon the LOC
       constraint 'P22'. It is recommended that you declare this BUFG explicitedly
       in your design. Note that for certain device families the output of a BUFG
       constraint can not drive a gated clock, and the BUFG constraint will be
       ignored.
    INFO:Cpld - Inferring BUFG constraint for signal 'rw' based upon the LOC
       constraint 'P23'. It is recommended that you declare this BUFG explicitedly
       in your design. Note that for certain device families the output of a BUFG
       constraint can not drive a gated clock, and the BUFG constraint will be
       ignored.
    WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'rw_IBUF' is
       ignored. Most likely the signal is gated and therefore cannot be used as a
       global control signal.
    WARNING:Cpld:1239 - The global clock designation (BUFG) on signal
       'd7_ram_rom_IOBUFE' is ignored. Most likely the signal is gated and therefore
       cannot be used as a global control signal.
    *************************  Summary of Mapped Logic  ************************

    ** 52 Outputs **

    Signal                                                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                                                              Pts   Inps          No.  Type    Use     Mode Rate State
    rom_ce                                                            8     13    FB1_3   12   I/O     O       LOW  SLOW
    data<0>                                                           8     20    FB1_6   14   I/O     I/O     LOW  SLOW
    data<2>                                                           7     19    FB1_8   15   I/O     I/O     LOW  SLOW
    data<1>                                                           6     18    FB1_9   16   I/O     I/O     LOW  SLOW
    data<6>                                                           2     10    FB1_11  17   I/O     I/O     LOW  SLOW
    data<5>                                                           4     13    FB1_12  18   I/O     I/O     LOW  SLOW
    data<4>                                                           5     14    FB1_14  19   I/O     I/O     LOW  SLOW
    data<3>                                                           7     19    FB1_15  20   I/O     I/O     LOW  SLOW
    data<7>                                                           14    21    FB1_17  22   GCK/I/O I/O     LOW  SLOW
    ram_rom_adr<14>                                                   12    17    FB2_5   1    GTS/I/O O       LOW  SLOW
    ram_rom_adr<13>                                                   12    17    FB2_6   2    GTS/I/O O       LOW  SLOW
    turbo_speed_out                                                   3     8     FB2_8   3    GTS/I/O O       LOW  SLOW
    ram_rom_adr<9>                                                    3     9     FB2_12  7    I/O     O       LOW  SLOW
    io_1050                                                           7     10    FB3_5   24   I/O     O       LOW  SLOW
    ram_rom_adr<11>                                                   11    12    FB3_9   28   I/O     O       LOW  SLOW
    ram_rom_adr<8>                                                    8     10    FB3_11  29   I/O     O       LOW  SLOW
    ram_rom_adr<12>                                                   22    17    FB3_17  34   I/O     O       LOW  SLOW
    track_lo_out<3>                                                   1     1     FB4_2   87   I/O     O       LOW  SLOW
    track_lo_out<2>                                                   1     1     FB4_5   89   I/O     O       LOW  SLOW
    track_lo_out<1>                                                   1     1     FB4_6   90   I/O     O       LOW  SLOW
    track_lo_out<0>                                                   1     1     FB4_8   91   I/O     O       LOW  SLOW
    ram_rom_adr<18>                                                   9     19    FB4_12  94   I/O     O       LOW  SLOW
    ram_rom_adr<17>                                                   8     19    FB4_14  95   I/O     O       LOW  SLOW
    ram_rom_adr<16>                                                   8     19    FB4_15  96   I/O     O       LOW  SLOW
    ram_rom_adr<15>                                                   16    19    FB4_17  97   I/O     O       LOW  SLOW
    ram_rom_adr<10>                                                   3     8     FB5_11  41   I/O     O       LOW  SLOW
    ram_ce                                                            15    18    FB5_12  42   I/O     O       LOW  SLOW
    d7_ram_rom                                                        2     4     FB5_15  46   I/O     I/O     LOW  SLOW
    ram_rom_oe                                                        1     2     FB5_17  49   I/O     O       LOW  SLOW
    track_hi_out<5>                                                   1     1     FB6_2   74   I/O     O       LOW  SLOW
    track_hi_out<4>                                                   1     1     FB6_5   76   I/O     O       LOW  SLOW
    track_hi_out<3>                                                   1     1     FB6_6   77   I/O     O       LOW  SLOW
    track_hi_out<2>                                                   1     1     FB6_8   78   I/O     O       LOW  SLOW
    track_hi_out<1>                                                   1     1     FB6_9   79   I/O     O       LOW  SLOW
    track_hi_out<0>                                                   1     1     FB6_12  81   I/O     O       LOW  SLOW
    track_lo_out<6>                                                   1     1     FB6_14  82   I/O     O       LOW  SLOW
    track_lo_out<5>                                                   1     1     FB6_15  85   I/O     O       LOW  SLOW
    track_lo_out<4>                                                   1     1     FB6_17  86   I/O     O       LOW  SLOW
    ram_rom_we                                                        1     2     FB7_2   50   I/O     O       LOW  SLOW
    fdc_write_out                                                     3     7     FB7_5   52   I/O     O       LOW  SLOW

    Signal                                                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                                                              Pts   Inps          No.  Type    Use     Mode Rate State
    riot_ready_inout                                                  2     5     FB7_9   55   I/O     I/O     LOW  SLOW
    cfg_led                                                           2     4     FB7_11  56   I/O     O       LOW  SLOW RESET
    i2c_clk_pin                                                       1     1     FB7_14  59   I/O     O       LOW  SLOW
    i2c_data_pin                                                      1     1     FB7_15  60   I/O     I/O     LOW  SLOW
    centronics_data                                                   4     26    FB8_5   64   I/O     O       LOW  SLOW SET
    centronics_strobe                                                 8     12    FB8_6   65   I/O     O       LOW  SLOW SET
    centronics_clk                                                    4     26    FB8_8   66   I/O     O       LOW  SLOW SET
    summer                                                            2     11    FB8_9   67   I/O     O       LOW  SLOW RESET
    density_out<2>                                                    1     1     FB8_11  68   I/O     O       LOW  SLOW
    density_out<1>                                                    1     1     FB8_12  70   I/O     O       LOW  SLOW
    density_out<0>                                                    1     1     FB8_14  71   I/O     O       LOW  SLOW
    track_hi_out<6>                                                   1     1     FB8_15  72   I/O     O       LOW  SLOW

    ** 79 Buried Nodes **

    Signal                                                            Total Total Loc     Pwr  Reg Init
    Name                                                              Pts   Inps          Mode State
    $OpTx$FX_DC$617                                                   9     14    FB1_1   LOW
    N76/N76_D2                                                        2     7     FB1_4   LOW
    $OpTx$FX_DC$571                                                   2     5     FB1_5   LOW
    $OpTx$FX_DC$551                                                   2     2     FB1_7   LOW
    data_7_mux0000/data_7_mux0000_TRST                                4     12    FB1_10  LOW
    check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2  5     8     FB1_13  LOW
    $OpTx$INV$546                                                     3     9     FB1_16  LOW
    track_lo<1>                                                       7     17    FB2_1   LOW  SET
    reset                                                             1     1     FB2_2   LOW  RESET
    ram_bank_5                                                        2     12    FB2_7   LOW  RESET
    track_hi<1>                                                       3     11    FB2_9   LOW  SET
    ram_bank_1                                                        3     14    FB2_10  LOW  RESET
    density<1>                                                        4     15    FB2_11  LOW  SET
    density<0>                                                        5     16    FB2_13  LOW  SET
    track_lo<6>                                                       6     18    FB2_14  LOW  SET
    track_lo<2>                                                       6     17    FB2_16  LOW  SET
    track_lo<5>                                                       7     18    FB2_17  LOW  SET
    track_lo<3>                                                       7     17    FB2_18  LOW  SET
    $OpTx$FX_DC$602                                                   5     11    FB3_1   LOW
    i2c_clk_and0000/i2c_clk_and0000_D2                                1     14    FB3_2   LOW
    data_0_cmp_eq0006/data_0_cmp_eq0006_D2                            1     16    FB3_3   LOW
    happy_a12__or0001/happy_a12__or0001_D2                            2     15    FB3_4   LOW
    $OpTx$FX_DC$601                                                   3     10    FB3_6   LOW
    track_hi<6>                                                       4     15    FB3_7   LOW  SET
    track_hi<3>                                                       4     16    FB3_10  LOW  SET
    track_hi<2>                                                       4     16    FB3_12  LOW  SET
    track_hi<0>                                                       4     16    FB3_13  LOW  SET
    track_hi<5>                                                       5     15    FB3_14  LOW  SET
    track_lo<0>                                                       7     17    FB4_1   LOW  SET
    ram_bank_4                                                        3     14    FB4_3   LOW  RESET
    ram_bank_3                                                        3     14    FB4_4   LOW  RESET
    ram_bank_2                                                        3     14    FB4_7   LOW  RESET
    ram_bank_0                                                        3     14    FB4_9   LOW  RESET
    track_lo<4>                                                       6     18    FB4_10  LOW  SET
    turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2              2     8     FB5_1   LOW
    rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2                2     6     FB5_2   LOW
    floppy_mode<3>                                                    2     6     FB5_3   LOW  RESET
    floppy_mode<2>                                                    2     6     FB5_4   LOW  RESET
    ms_write_enable                                                   3     8     FB5_5   LOW  SET
    ms_speed_select                                                   3     8     FB5_6   LOW  SET

    Signal                                                            Total Total Loc     Pwr  Reg Init
    Name                                                              Pts   Inps          Mode State
    i2c_data                                                          3     8     FB5_7   LOW  SET
    i2c_clk                                                           3     8     FB5_8   LOW  SET
    floppy_mode<1>                                                    3     7     FB5_9   LOW  SET
    floppy_mode<0>                                                    3     7     FB5_10  LOW  SET
    N2/N2_D2                                                          3     10    FB5_13  LOW
    N11/N11_D2                                                        3     10    FB5_14  LOW
    track_hi<4>                                                       4     14    FB5_16  LOW  SET
    density<2>                                                        4     15    FB5_18  LOW  SET
    reset_sync                                                        1     1     FB6_1   LOW  RESET
    N120/N120_D2                                                      1     4     FB6_3   LOW
    rom_source_is_ram                                                 2     4     FB6_4   LOW  RESET
    rom_base_bank_6                                                   2     4     FB6_7   LOW  SET
    rom_base_bank_5                                                   2     4     FB6_10  LOW  SET
    rom_base_bank_4                                                   2     4     FB6_11  LOW  SET
    rom_base_bank_3                                                   2     4     FB6_13  LOW  SET
    rom_base_bank_2                                                   2     4     FB6_16  LOW  RESET
    happy_a12                                                         3     7     FB6_18  LOW  RESET
    turbo_rom_adr<12>                                                 2     4     FB7_1   LOW  SET
    turbo_rom_adr<11>                                                 2     5     FB7_3   LOW  SET
    rom_base_bank_1                                                   2     4     FB7_4   LOW  RESET
    rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2                2     5     FB7_6   LOW
    rom_base_bank_0                                                   2     4     FB7_7   LOW  RESET
    rom_bank_c000_enable<0>                                           2     4     FB7_8   LOW  RESET
    rom_bank_c000_5                                                   2     4     FB7_10  LOW  RESET
    rom_bank_c000_4                                                   2     4     FB7_12  LOW  RESET
    rom_bank_c000_3                                                   2     4     FB7_13  LOW  RESET
    rom_bank_c000_2                                                   2     4     FB7_16  LOW  RESET
    rom_bank_c000_1                                                   2     4     FB7_17  LOW  RESET
    rom_bank_c000_0                                                   2     4     FB7_18  LOW  RESET
    data_0_cmp_eq0005/data_0_cmp_eq0005_D2                            1     16    FB8_1   LOW
    data_0_cmp_eq0004/data_0_cmp_eq0004_D2                            1     16    FB8_2   LOW
    data_0_cmp_eq0002/data_0_cmp_eq0002_D2                            1     16    FB8_3   LOW
    data_0_cmp_eq0001/data_0_cmp_eq0001_D2                            1     16    FB8_4   LOW
    data_0_cmp_eq0000/data_0_cmp_eq0000_D2                            1     16    FB8_7   LOW
    $OpTx$FX_DC$640                                                   1     19    FB8_10  LOW
    $OpTx$FX_DC$624                                                   1     16    FB8_13  LOW
    $OpTx$FX_DC$555                                                   1     16    FB8_16  LOW
    $OpTx$INV$547                                                     2     20    FB8_17  LOW
    $OpTx$INV$548                                                     5     16    FB8_18  LOW

    ** 29 Inputs **

    Signal                                                            Loc     Pin  Pin     Pin
    Name                                                                      No.  Type    Use
    adr<1>                                                            FB1_2   11   I/O     I
    adr<0>                                                            FB1_5   13   I/O     I
    reset_in                                                          FB2_2   99   GSR/I/O I
    turbo_speed_in                                                    FB2_9   4    GTS/I/O I
    adr<5>                                                            FB2_11  6    I/O     I
    adr<4>                                                            FB2_14  8    I/O     I
    adr<3>                                                            FB2_15  9    I/O     I
    adr<2>                                                            FB2_17  10   I/O     I
    rw                                                                FB3_2   23   GCK/I/O I
    adr<6>                                                            FB3_6   25   I/O     I
    phi2                                                              FB3_8   27   GCK/I/O GCK/I
    adr<7>                                                            FB3_12  30   I/O     I
    adr<8>                                                            FB3_14  32   I/O     I
    adr<9>                                                            FB3_15  33   I/O     I
    cfg_enc_a                                                         FB4_9   92   I/O     I
    cfg_enc_b                                                         FB4_11  93   I/O     I
    adr<10>                                                           FB5_2   35   I/O     I
    adr<11>                                                           FB5_5   36   I/O     I
    adr<13>                                                           FB5_6   37   I/O     I
    adr<14>                                                           FB5_8   39   I/O     I
    adr<15>                                                           FB5_9   40   I/O     I
    adr<12>                                                           FB5_14  43   I/O     I
    cfg_sw1                                                           FB6_11  80   I/O     I
    archiver_a11                                                      FB7_6   53   I/O     I
    fdc_write_in                                                      FB7_8   54   I/O     I
    riot_ready_in                                                     FB7_12  58   I/O     I
    cfg_sw2                                                           FB7_17  61   I/O     I
    centronics_busy                                                   FB8_2   63   I/O     I
    cfg_enc_ok                                                        FB8_17  73   I/O     I

    Legend:
    Pin No. - ~ - User Assigned
    **************************  Function Block Details  ************************
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X            - Signal used as input to the macrocell logic.
    Pin No.      - ~  - User Assigned
    *********************************** FB1  ***********************************
    Number of function block inputs used/remaining:               53/1
    Number of signals used by logic mapping into function block:  53
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    $OpTx$FX_DC$617       9       5<- /\1   0     FB1_1         (b)     (b)
    (unused)              0       0   /\5   0     FB1_2   11    I/O     I
    rom_ce                8       3<-   0   0     FB1_3   12    I/O     O
    N76/N76_D2            2       0   /\3   0     FB1_4         (b)     (b)
    $OpTx$FX_DC$571       2       0   \/3   0     FB1_5   13    I/O     I
    data<0>               8       3<-   0   0     FB1_6   14    I/O     I/O
    $OpTx$FX_DC$551       2       0   \/2   1     FB1_7         (b)     (b)
    data<2>               7       2<-   0   0     FB1_8   15    I/O     I/O
    data<1>               6       1<-   0   0     FB1_9   16    I/O     I/O
    data_7_mux0000/data_7_mux0000_TRST
                          4       0   /\1   0     FB1_10        (b)     (b)
    data<6>               2       0   \/2   1     FB1_11  17    I/O     I/O
    data<5>               4       2<- \/3   0     FB1_12  18    I/O     I/O
    check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2
                          5       3<- \/3   0     FB1_13        (b)     (b)
    data<4>               5       3<- \/3   0     FB1_14  19    I/O     I/O
    data<3>               7       3<- \/1   0     FB1_15  20    I/O     I/O
    $OpTx$INV$546         3       1<- \/3   0     FB1_16        (b)     (b)
    data<7>              14       9<-   0   0     FB1_17  22    GCK/I/O I/O
    (unused)              0       0   /\5   0     FB1_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$551   19: data_0_cmp_eq0000/data_0_cmp_eq0000_D2  37: rom_bank_c000_0
      2: $OpTx$FX_DC$555   20: data_0_cmp_eq0001/data_0_cmp_eq0001_D2  38: rom_bank_c000_1
      3: $OpTx$FX_DC$617   21: data_0_cmp_eq0002/data_0_cmp_eq0002_D2  39: rom_bank_c000_2
      4: $OpTx$INV$548     22: data_0_cmp_eq0004/data_0_cmp_eq0004_D2  40: rom_bank_c000_3
      5: i2c_data_pin.PIN  23: data_0_cmp_eq0005/data_0_cmp_eq0005_D2  41: rom_bank_c000_4
      6: d7_ram_rom.PIN    24: data_0_cmp_eq0006/data_0_cmp_eq0006_D2  42: rom_bank_c000_5
      7: adr<11>           25: data_7_mux0000/data_7_mux0000_TRST      43: rom_bank_c000_enable<0>
      8: adr<12>           26: fdc_write_in                            44: rom_base_bank_0
      9: adr<13>           27: floppy_mode<0>                          45: rom_base_bank_1
     10: adr<14>           28: floppy_mode<1>                          46: rom_base_bank_2
     11: adr<15>           29: floppy_mode<2>                          47: rom_base_bank_3
     12: archiver_a11      30: floppy_mode<3>                          48: rom_base_bank_4
     13: centronics_busy   31: i2c_clk_and0000/i2c_clk_and0000_D2      49: rom_base_bank_5
     14: cfg_enc_a         32: ms_speed_select                         50: rom_base_bank_6
     15: cfg_enc_b         33: ms_write_enable                         51: rom_source_is_ram
     16: cfg_enc_ok        34: phi2                                    52: rw
     17: cfg_sw1           35: ram_ce                                  53: turbo_speed_in
     18: cfg_sw2           36: riot_ready_in

    Signal                        1         2         3         4         5         6 FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
    $OpTx$FX_DC$617      X.....XXXXX...............XXXX....X.......X.......XX........ 14
    rom_ce               X.....XXXXX...............XXXX............X.......XX........ 13
    N76/N76_D2           X.......XXX.................XX............X................. 7
    $OpTx$FX_DC$571      ........X.................XXXX.............................. 5
    data<0>              XX.X.........X....XXXXXX..X.XX.XXX..X......X.......XX....... 20
    $OpTx$FX_DC$551      ..........................XX................................ 2
    data<2>              XX.X...........X..XXXXXX....XX...X.X..X...X..XX....X........ 19
    data<1>              XX.X.......X..X...XXXXXX...XXX...X...X......X......X........ 18
    data_7_mux0000/data_7_mux0000_TRST
                         X.XX..XX..................XXXXX..X.................X........ 12
    data<6>              X..X..............XXX.......XX...X...............X.X........ 10
    data<5>              X..X..............XXX.......XX...X.......XX.....XX.X........ 13
    check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2
                         .......XXXX...............XXXX.............................. 8
    data<4>              X..X.............XXXX.......XX...X......X.X....XX..X........ 14
    data<3>              XX.X............X.XXXXXX.X..XX...X.....X..X...XX...X........ 19
    $OpTx$INV$546        .......XXXX...............XXXX.....................X........ 9
    data<7>              XX.XXXXX....X.....XXXX..X.XXXXX...........X.......XX........ 21
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    *********************************** FB2  ***********************************
    Number of function block inputs used/remaining:               50/4
    Number of signals used by logic mapping into function block:  50
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    track_lo<1>           7       4<- /\2   0     FB2_1         (b)     (b)
    reset                 1       0   /\4   0     FB2_2   99    GSR/I/O I
    (unused)              0       0   \/5   0     FB2_3         (b)     (b)
    (unused)              0       0   \/5   0     FB2_4         (b)     (b)
    ram_rom_adr<14>      12      10<- \/3   0     FB2_5   1     GTS/I/O O
    ram_rom_adr<13>      12       7<-   0   0     FB2_6   2     GTS/I/O O
    ram_bank_5            2       1<- /\4   0     FB2_7         (b)     (b)
    turbo_speed_out       3       0   /\1   1     FB2_8   3     GTS/I/O O
    track_hi<1>           3       0     0   2     FB2_9   4     GTS/I/O I
    ram_bank_1            3       0     0   2     FB2_10        (b)     (b)
    density<1>            4       0     0   1     FB2_11  6     I/O     I
    ram_rom_adr<9>        3       0   \/1   1     FB2_12  7     I/O     O
    density<0>            5       1<- \/1   0     FB2_13        (b)     (b)
    track_lo<6>           6       1<-   0   0     FB2_14  8     I/O     I
    (unused)              0       0   \/3   2     FB2_15  9     I/O     I
    track_lo<2>           6       3<- \/2   0     FB2_16        (b)     (b)
    track_lo<5>           7       2<-   0   0     FB2_17  10    I/O     I
    track_lo<3>           7       2<-   0   0     FB2_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$551       18: adr<12>           35: ram_bank_5
      2: $OpTx$FX_DC$571       19: adr<13>           36: reset
      3: $OpTx$FX_DC$601       20: adr<14>           37: reset_sync
      4: $OpTx$FX_DC$602       21: adr<15>           38: rom_bank_c000_0
      5: $OpTx$INV$546         22: adr<1>            39: rom_bank_c000_1
      6: N11/N11_D2            23: adr<7>            40: rom_base_bank_1
      7: N120/N120_D2          24: adr<9>            41: rom_base_bank_2
      8: N2/N2_D2              25: data<7>.PIN       42: rom_source_is_ram
      9: riot_ready_inout.PIN  26: density<0>        43: rw
     10: data<6>.PIN           27: density<1>        44: track_hi<1>
     11: data<5>.PIN           28: floppy_mode<0>    45: track_lo<1>
     12: data<3>.PIN           29: floppy_mode<1>    46: track_lo<2>
     13: data<2>.PIN           30: floppy_mode<2>    47: track_lo<3>
     14: data<1>.PIN           31: floppy_mode<3>    48: track_lo<5>
     15: data<0>.PIN           32: ms_speed_select   49: track_lo<6>
     16: adr<0>                33: ram_bank_0        50: turbo_speed_in
     17: adr<10>               34: ram_bank_1

    Signal                        1         2         3         4         5         6 FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
    track_lo<1>          .X...X.....XXXXX...XXX.....XXXX....X......X.X............... 17
    reset                ....................................X....................... 1
    ram_rom_adr<14>      X..X..X.........XXXXX.X....XXXX..X....X.XX.................. 17
    ram_rom_adr<13>      X..X..X.........XXXXX.X....XXXX.X....X.X.X.................. 17
    ram_bank_5           X...X.....X......XXXX........XX...XX......X................. 12
    turbo_speed_out      X.......X..................XXXXX.................X.......... 8
    track_hi<1>          .X.....X.....X.X...XXX........X....X......XX................ 11
    ram_bank_1           X...X........X...XXXX......XXXX..X.X......X................. 14
    density<1>           .XX..........X.X...XXX..X.XXXXX....X......X................. 15
    ram_rom_adr<9>       ......X.........XX....XX...XXXX............................. 9
    density<0>           .XX......X....XX...XXX..XX.XXXX....X......X................. 16
    track_lo<6>          .X...X...X.XXXXX...XXX.....XXXX....X......X.....X........... 18
    track_lo<2>          .X...X.....XXXXX...XXX.....XXXX....X......X..X.............. 17
    track_lo<5>          .X...X....XXXXXX...XXX.....XXXX....X......X....X............ 18
    track_lo<3>          .X...X.....XXXXX...XXX.....XXXX....X......X...X............. 17
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    *********************************** FB3  ***********************************
    Number of function block inputs used/remaining:               43/11
    Number of signals used by logic mapping into function block:  43
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    $OpTx$FX_DC$602       5       2<- /\2   0     FB3_1         (b)     (b)
    i2c_clk_and0000/i2c_clk_and0000_D2
                          1       0   /\2   2     FB3_2   23    GCK/I/O I
    data_0_cmp_eq0006/data_0_cmp_eq0006_D2
                          1       0     0   4     FB3_3         (b)     (b)
    happy_a12__or0001/happy_a12__or0001_D2
                          2       0     0   3     FB3_4         (b)     (b)
    io_1050               7       2<-   0   0     FB3_5   24    I/O     O
    $OpTx$FX_DC$601       3       0   /\2   0     FB3_6   25    I/O     I
    track_hi<6>           4       0   \/1   0     FB3_7         (b)     (b)
    (unused)              0       0   \/5   0     FB3_8   27    GCK/I/O GCK/I
    ram_rom_adr<11>      11       6<-   0   0     FB3_9   28    I/O     O
    track_hi<3>           4       0   \/1   0     FB3_10        (b)     (b)
    ram_rom_adr<8>        8       3<-   0   0     FB3_11  29    I/O     O
    track_hi<2>           4       1<- /\2   0     FB3_12  30    I/O     I
    track_hi<0>           4       0   /\1   0     FB3_13        (b)     (b)
    track_hi<5>           5       0     0   0     FB3_14  32    I/O     I
    (unused)              0       0   \/5   0     FB3_15  33    I/O     I
    (unused)              0       0   \/5   0     FB3_16        (b)     (b)
    ram_rom_adr<12>      22      17<-   0   0     FB3_17  34    I/O     O
    (unused)              0       0   /\5   0     FB3_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$571   16: adr<15>                                                           30: floppy_mode<2>
      2: N120/N120_D2      17: adr<1>                                                            31: floppy_mode<3>
      3: N2/N2_D2          18: adr<2>                                                            32: happy_a12
      4: data<6>.PIN       19: adr<3>                                                            33: reset
      5: data<5>.PIN       20: adr<4>                                                            34: rom_base_bank_0
      6: data<4>.PIN       21: adr<5>                                                            35: rom_source_is_ram
      7: data<3>.PIN       22: adr<6>                                                            36: rw
      8: data<2>.PIN       23: adr<7>                                                            37: track_hi<0>
      9: data<0>.PIN       24: adr<8>                                                            38: track_hi<2>
     10: adr<0>            25: adr<9>                                                            39: track_hi<3>
     11: adr<10>           26: archiver_a11                                                      40: track_hi<5>
     12: adr<11>           27: check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2  41: track_hi<6>
     13: adr<12>           28: floppy_mode<0>                                                    42: turbo_rom_adr<11>
     14: adr<13>           29: floppy_mode<1>                                                    43: turbo_rom_adr<12>
     15: adr<14>

    Signal                        1         2         3         4         5 FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
    $OpTx$FX_DC$602      ..........XXXXXX...........XXXX....X.............. 11
    i2c_clk_and0000/i2c_clk_and0000_D2
                         ..........XXXXXX.XXXXXXXX......................... 14
    data_0_cmp_eq0006/data_0_cmp_eq0006_D2
                         .........XXXXXXXXXXXXXXXX......................... 16
    happy_a12__or0001/happy_a12__or0001_D2
                         ..........XX..XX...XXXXXX..XXXX.X................. 15
    io_1050              ..........XXX.........X.X.XXXXX................... 10
    $OpTx$FX_DC$601      .........X...XXXX..........XXXX....X.............. 10
    track_hi<6>          X.XXX....X....XXX..........XXXX.X..X....X......... 15
    ram_rom_adr<11>      .X........XXX.........X..X.XXXX....X.....X........ 12
    track_hi<3>          X.X.XXX..X....XXX..........XXXX.X..X..X........... 16
    ram_rom_adr<8>       .X........X.X.........XXX..XXXX................... 10
    track_hi<2>          X.X.XX.X.X....XXX..........XXXX.X..X.X............ 16
    track_hi<0>          X.X.XX..XX....XXX..........XXXX.X..XX............. 16
    track_hi<5>          X.X.XX...X....XXX..........XXXX.X..X...X.......... 15
    ram_rom_adr<12>      .X........XXXXXX......X....XXXXX.XXX......X....... 17
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    *********************************** FB4  ***********************************
    Number of function block inputs used/remaining:               47/7
    Number of signals used by logic mapping into function block:  47
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    track_lo<0>           7       3<- /\1   0     FB4_1         (b)     (b)
    track_lo_out<3>       1       0   /\3   1     FB4_2   87    I/O     O
    ram_bank_4            3       0     0   2     FB4_3         (b)     (b)
    ram_bank_3            3       0     0   2     FB4_4         (b)     (b)
    track_lo_out<2>       1       0     0   4     FB4_5   89    I/O     O
    track_lo_out<1>       1       0     0   4     FB4_6   90    I/O     O
    ram_bank_2            3       0     0   2     FB4_7         (b)     (b)
    track_lo_out<0>       1       0     0   4     FB4_8   91    I/O     O
    ram_bank_0            3       0   \/1   1     FB4_9   92    I/O     I
    track_lo<4>           6       1<-   0   0     FB4_10        (b)     (b)
    (unused)              0       0   \/5   0     FB4_11  93    I/O     I
    ram_rom_adr<18>       9       5<- \/1   0     FB4_12  94    I/O     O
    (unused)              0       0   \/5   0     FB4_13        (b)     (b)
    ram_rom_adr<17>       8       6<- \/3   0     FB4_14  95    I/O     O
    ram_rom_adr<16>       8       3<-   0   0     FB4_15  96    I/O     O
    (unused)              0       0   \/5   0     FB4_16        (b)     (b)
    ram_rom_adr<15>      16      11<-   0   0     FB4_17  97    I/O     O
    (unused)              0       0   /\5   0     FB4_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$551   17: adr<13>           33: rom_bank_c000_3
      2: $OpTx$FX_DC$571   18: adr<14>           34: rom_bank_c000_4
      3: $OpTx$FX_DC$602   19: adr<15>           35: rom_bank_c000_5
      4: $OpTx$INV$546     20: adr<1>            36: rom_bank_c000_enable<0>
      5: N11/N11_D2        21: adr<7>            37: rom_base_bank_3
      6: N120/N120_D2      22: floppy_mode<0>    38: rom_base_bank_4
      7: data<4>.PIN       23: floppy_mode<1>    39: rom_base_bank_5
      8: data<3>.PIN       24: floppy_mode<2>    40: rom_base_bank_6
      9: data<2>.PIN       25: floppy_mode<3>    41: rom_source_is_ram
     10: data<1>.PIN       26: ram_bank_0        42: rw
     11: data<0>.PIN       27: ram_bank_2        43: track_lo<0>
     12: N76/N76_D2        28: ram_bank_3        44: track_lo<1>
     13: adr<0>            29: ram_bank_4        45: track_lo<2>
     14: adr<10>           30: ram_bank_5        46: track_lo<3>
     15: adr<11>           31: reset             47: track_lo<4>
     16: adr<12>           32: rom_bank_c000_2

    Signal                        1         2         3         4         5 FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
    track_lo<0>          .X..X..XXXX.X....XXX.XXXX.....X..........XX....... 17
    track_lo_out<3>      .............................................X.... 1
    ram_bank_4           X..X..X........XXXX..XXXX...X.X..........X........ 14
    ram_bank_3           X..X...X.......XXXX..XXXX..X..X..........X........ 14
    track_lo_out<2>      ............................................X..... 1
    track_lo_out<1>      ...........................................X...... 1
    ram_bank_2           X..X....X......XXXX..XXXX.X...X..........X........ 14
    track_lo_out<0>      ..........................................X....... 1
    ram_bank_0           X..X......X....XXXX..XXXXX....X..........X........ 14
    track_lo<4>          .X..X.XXXXX.X....XXX.XXXX.....X..........X....X... 18
    ram_rom_adr<18>      X.X..X.....X.X.XXXX.XXXXX....X....XX...XX......... 19
    ram_rom_adr<17>      X.X..X.....X.X.XXXX.XXXXX...X....X.X..X.X......... 19
    ram_rom_adr<16>      X.X..X.....X.X.XXXX.XXXXX..X....X..X.X..X......... 19
    ram_rom_adr<15>      X....X.......XXXXXX.XXXXX.X....X...XX...XX........ 19
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    *********************************** FB5  ***********************************
    Number of function block inputs used/remaining:               46/8
    Number of signals used by logic mapping into function block:  46
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2
                          2       0     0   3     FB5_1         (b)     (b)
    rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2
                          2       0     0   3     FB5_2   35    I/O     I
    floppy_mode<3>        2       0     0   3     FB5_3         (b)     (b)
    floppy_mode<2>        2       0     0   3     FB5_4         (b)     (b)
    ms_write_enable       3       0     0   2     FB5_5   36    I/O     I
    ms_speed_select       3       0     0   2     FB5_6   37    I/O     I
    i2c_data              3       0     0   2     FB5_7         (b)     (b)
    i2c_clk               3       0     0   2     FB5_8   39    I/O     I
    floppy_mode<1>        3       0   \/1   1     FB5_9   40    I/O     I
    floppy_mode<0>        3       1<- \/3   0     FB5_10        (b)     (b)
    ram_rom_adr<10>       3       3<- \/5   0     FB5_11  41    I/O     O
    ram_ce               15      10<-   0   0     FB5_12  42    I/O     O
    N2/N2_D2              3       3<- /\5   0     FB5_13        (b)     (b)
    N11/N11_D2            3       1<- /\3   0     FB5_14  43    I/O     I
    d7_ram_rom            2       0   /\1   2     FB5_15  46    I/O     I/O
    track_hi<4>           4       0     0   1     FB5_16        (b)     (b)
    ram_rom_oe            1       0     0   4     FB5_17  49    I/O     O
    density<2>            4       0     0   1     FB5_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$551   17: adr<10>                                 32: floppy_mode<2>
      2: $OpTx$FX_DC$555   18: adr<11>                                 33: floppy_mode<3>
      3: $OpTx$FX_DC$571   19: adr<12>                                 34: i2c_clk
      4: $OpTx$FX_DC$601   20: adr<13>                                 35: i2c_clk_and0000/i2c_clk_and0000_D2
      5: $OpTx$FX_DC$602   21: adr<14>                                 36: i2c_data
      6: $OpTx$FX_DC$617   22: adr<15>                                 37: ms_speed_select
      7: N120/N120_D2      23: adr<1>                                  38: ms_write_enable
      8: N2/N2_D2          24: adr<7>                                  39: phi2
      9: d7_ram_rom.PIN    25: data<7>.PIN                             40: ram_bank_3
     10: data<6>.PIN       26: data_0_cmp_eq0001/data_0_cmp_eq0001_D2  41: ram_bank_4
     11: data<4>.PIN       27: data_0_cmp_eq0005/data_0_cmp_eq0005_D2  42: reset
     12: data<3>.PIN       28: data_0_cmp_eq0006/data_0_cmp_eq0006_D2  43: rom_bank_c000_enable<0>
     13: data<2>.PIN       29: density<2>                              44: rom_source_is_ram
     14: data<1>.PIN       30: floppy_mode<0>                          45: rw
     15: data<0>.PIN       31: floppy_mode<1>                          46: track_hi<4>
     16: adr<0>

    Signal                        1         2         3         4         5 FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
    turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2
                         ........X........XX..........XXXX........X........ 8
    rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2
                         X........................X.....XX........X..X..... 6
    floppy_mode<3>       XX.........X...................XX........X........ 6
    floppy_mode<2>       XX..........X..................XX........X........ 6
    ms_write_enable      X.............X............X...XX....X...X..X..... 8
    ms_speed_select      X.............X...........X....XX...X....X..X..... 8
    i2c_data             X.....................X........XX.XX.....X..X..... 8
    i2c_clk              X..............X...............XXXX......X..X..... 8
    floppy_mode<1>       XX...........X................XXX........X........ 7
    floppy_mode<0>       XX............X..............X.XX........X........ 7
    ram_rom_adr<10>      ......X.........X.X....X.....XXXX................. 8
    ram_ce               X...X.X.........X.XXXX.X.....XXXX......XX.XXX..... 18
    N2/N2_D2             ...............X...XXXX......XXXX...........X..... 10
    N11/N11_D2           ...............X...XXXX......XXXX...........X..... 10
    d7_ram_rom           .....X..................X.............X.....X..... 4
    track_hi<4>          ..X....X..X....X....XXX......XXXX........X..XX.... 14
    ram_rom_oe           ......................................X.....X..... 2
    density<2>           ..XX.....X..X..X....XXX.....XXXXX........X..X..... 15
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    *********************************** FB6  ***********************************
    Number of function block inputs used/remaining:               34/20
    Number of signals used by logic mapping into function block:  34
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    reset_sync            1       0     0   4     FB6_1         (b)     (b)
    track_hi_out<5>       1       0     0   4     FB6_2   74    I/O     O
    N120/N120_D2          1       0     0   4     FB6_3         (b)     (b)
    rom_source_is_ram     2       0     0   3     FB6_4         (b)     (b)
    track_hi_out<4>       1       0     0   4     FB6_5   76    I/O     O
    track_hi_out<3>       1       0     0   4     FB6_6   77    I/O     O
    rom_base_bank_6       2       0     0   3     FB6_7         (b)     (b)
    track_hi_out<2>       1       0     0   4     FB6_8   78    I/O     O
    track_hi_out<1>       1       0     0   4     FB6_9   79    I/O     O
    rom_base_bank_5       2       0     0   3     FB6_10        (b)     (b)
    rom_base_bank_4       2       0     0   3     FB6_11  80    I/O     I
    track_hi_out<0>       1       0     0   4     FB6_12  81    I/O     O
    rom_base_bank_3       2       0     0   3     FB6_13        (b)     (b)
    track_lo_out<6>       1       0     0   4     FB6_14  82    I/O     O
    track_lo_out<5>       1       0     0   4     FB6_15  85    I/O     O
    rom_base_bank_2       2       0     0   3     FB6_16        (b)     (b)
    track_lo_out<4>       1       0     0   4     FB6_17  86    I/O     O
    happy_a12             3       0     0   2     FB6_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: data<6>.PIN       13: check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2  24: rom_base_bank_6
      2: data<5>.PIN       14: data<7>.PIN                                                       25: rom_source_is_ram
      3: data<4>.PIN       15: happy_a12                                                         26: track_hi<0>
      4: data<3>.PIN       16: happy_a12__or0001/happy_a12__or0001_D2                            27: track_hi<1>
      5: data<2>.PIN       17: reset                                                             28: track_hi<2>
      6: adr<0>            18: reset_in                                                          29: track_hi<3>
      7: adr<10>           19: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2                30: track_hi<4>
      8: adr<1>            20: rom_base_bank_2                                                   31: track_hi<5>
      9: adr<2>            21: rom_base_bank_3                                                   32: track_lo<4>
     10: adr<3>            22: rom_base_bank_4                                                   33: track_lo<5>
     11: adr<7>            23: rom_base_bank_5                                                   34: track_lo<6>
     12: adr<9>

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    reset_sync           .................X...................... 1
    track_hi_out<5>      ..............................X......... 1
    N120/N120_D2         ......X...XXX........................... 4
    rom_source_is_ram    .............X..X.X.....X............... 4
    track_hi_out<4>      .............................X.......... 1
    track_hi_out<3>      ............................X........... 1
    rom_base_bank_6      X...............X.X....X................ 4
    track_hi_out<2>      ...........................X............ 1
    track_hi_out<1>      ..........................X............. 1
    rom_base_bank_5      .X..............X.X...X................. 4
    rom_base_bank_4      ..X.............X.X..X.................. 4
    track_hi_out<0>      .........................X.............. 1
    rom_base_bank_3      ...X............X.X.X................... 4
    track_lo_out<6>      .................................X...... 1
    track_lo_out<5>      ................................X....... 1
    rom_base_bank_2      ....X...........X.XX.................... 4
    track_lo_out<4>      ...............................X........ 1
    happy_a12            .....X.XXX....XXX....................... 7
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB7  ***********************************
    Number of function block inputs used/remaining:               39/15
    Number of signals used by logic mapping into function block:  39
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    turbo_rom_adr<12>     2       0     0   3     FB7_1         (b)     (b)
    ram_rom_we            1       0     0   4     FB7_2   50    I/O     O
    turbo_rom_adr<11>     2       0     0   3     FB7_3         (b)     (b)
    rom_base_bank_1       2       0     0   3     FB7_4         (b)     (b)
    fdc_write_out         3       0     0   2     FB7_5   52    I/O     O
    rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2
                          2       0     0   3     FB7_6   53    I/O     I
    rom_base_bank_0       2       0     0   3     FB7_7         (b)     (b)
    rom_bank_c000_enable<0>
                          2       0     0   3     FB7_8   54    I/O     I
    riot_ready_inout      2       0     0   3     FB7_9   55    I/O     I/O
    rom_bank_c000_5       2       0     0   3     FB7_10        (b)     (b)
    cfg_led               2       0     0   3     FB7_11  56    I/O     O
    rom_bank_c000_4       2       0     0   3     FB7_12  58    I/O     I
    rom_bank_c000_3       2       0     0   3     FB7_13        (b)     (b)
    i2c_clk_pin           1       0     0   4     FB7_14  59    I/O     O
    i2c_data_pin          1       0     0   4     FB7_15  60    I/O     I/O
    rom_bank_c000_2       2       0     0   3     FB7_16        (b)     (b)
    rom_bank_c000_1       2       0     0   3     FB7_17  61    I/O     I
    rom_bank_c000_0       2       0     0   3     FB7_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$551                         14: fdc_write_in                                        27: rom_bank_c000_1
      2: $OpTx$FX_DC$640                         15: floppy_mode<0>                                      28: rom_bank_c000_2
      3: data<6>.PIN                             16: floppy_mode<1>                                      29: rom_bank_c000_3
      4: data<5>.PIN                             17: floppy_mode<2>                                      30: rom_bank_c000_4
      5: data<4>.PIN                             18: floppy_mode<3>                                      31: rom_bank_c000_5
      6: data<3>.PIN                             19: i2c_clk                                             32: rom_bank_c000_enable<0>
      7: data<2>.PIN                             20: i2c_data                                            33: rom_base_bank_0
      8: data<1>.PIN                             21: ms_write_enable                                     34: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2
      9: data<0>.PIN                             22: phi2                                                35: rom_base_bank_1
     10: archiver_a11                            23: reset                                               36: rw
     11: cfg_led                                 24: riot_ready_in                                       37: turbo_rom_adr<11>
     12: data<7>.PIN                             25: rom_bank_c000_0                                     38: turbo_rom_adr<12>
     13: data_0_cmp_eq0002/data_0_cmp_eq0002_D2  26: rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2  39: turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    turbo_rom_adr<12>    ...X..................X..............XX. 4
    ram_rom_we           .....................X.............X.... 2
    turbo_rom_adr<11>    ..X.X.................X.............X.X. 5
    rom_base_bank_1      .......X..............X..........XX..... 4
    fdc_write_out        X........X...X.XXX..X................... 7
    rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2
                         X...........X...XX....X................. 5
    rom_base_bank_0      ........X.............X.........XX...... 4
    rom_bank_c000_enable<0>
                         ...........X..........X..X.....X........ 4
    riot_ready_inout     ..............XXXX.....X................ 5
    rom_bank_c000_5      ...X..................X..X....X......... 4
    cfg_led              .X......X.X...........X................. 4
    rom_bank_c000_4      ....X.................X..X...X.......... 4
    rom_bank_c000_3      .....X................X..X..X........... 4
    i2c_clk_pin          ..................X..................... 1
    i2c_data_pin         ...................X.................... 1
    rom_bank_c000_2      ......X...............X..X.X............ 4
    rom_bank_c000_1      .......X..............X..XX............. 4
    rom_bank_c000_0      ........X.............X.XX.............. 4
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB8  ***********************************
    Number of function block inputs used/remaining:               36/18
    Number of signals used by logic mapping into function block:  36
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    data_0_cmp_eq0005/data_0_cmp_eq0005_D2
                          1       0     0   4     FB8_1         (b)     (b)
    data_0_cmp_eq0004/data_0_cmp_eq0004_D2
                          1       0     0   4     FB8_2   63    I/O     I
    data_0_cmp_eq0002/data_0_cmp_eq0002_D2
                          1       0     0   4     FB8_3         (b)     (b)
    data_0_cmp_eq0001/data_0_cmp_eq0001_D2
                          1       0     0   4     FB8_4         (b)     (b)
    centronics_data       4       0   \/1   0     FB8_5   64    I/O     O
    centronics_strobe     8       3<-   0   0     FB8_6   65    I/O     O
    data_0_cmp_eq0000/data_0_cmp_eq0000_D2
                          1       0   /\2   2     FB8_7         (b)     (b)
    centronics_clk        4       0     0   1     FB8_8   66    I/O     O
    summer                2       0     0   3     FB8_9   67    I/O     O
    $OpTx$FX_DC$640       1       0     0   4     FB8_10        (b)     (b)
    density_out<2>        1       0     0   4     FB8_11  68    I/O     O
    density_out<1>        1       0     0   4     FB8_12  70    I/O     O
    $OpTx$FX_DC$624       1       0     0   4     FB8_13        (b)     (b)
    density_out<0>        1       0     0   4     FB8_14  71    I/O     O
    track_hi_out<6>       1       0     0   4     FB8_15  72    I/O     O
    $OpTx$FX_DC$555       1       0     0   4     FB8_16        (b)     (b)
    $OpTx$INV$547         2       0     0   3     FB8_17  73    I/O     I
    $OpTx$INV$548         5       0     0   0     FB8_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$551   13: adr<14>           25: centronics_data
      2: $OpTx$FX_DC$624   14: adr<15>           26: centronics_strobe
      3: $OpTx$INV$547     15: adr<1>            27: density<0>
      4: d7_ram_rom.PIN    16: adr<2>            28: density<1>
      5: data<6>.PIN       17: adr<3>            29: density<2>
      6: data<5>.PIN       18: adr<4>            30: floppy_mode<0>
      7: data<4>.PIN       19: adr<5>            31: floppy_mode<1>
      8: adr<0>            20: adr<6>            32: floppy_mode<2>
      9: adr<10>           21: adr<7>            33: floppy_mode<3>
     10: adr<11>           22: adr<8>            34: reset
     11: adr<12>           23: adr<9>            35: rw
     12: adr<13>           24: centronics_clk    36: track_hi<6>

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    data_0_cmp_eq0005/data_0_cmp_eq0005_D2
                         .......XXXXXXXXXXXXXXXX................. 16
    data_0_cmp_eq0004/data_0_cmp_eq0004_D2
                         .......XXXXXXXXXXXXXXXX................. 16
    data_0_cmp_eq0002/data_0_cmp_eq0002_D2
                         .......XXXXXXXXXXXXXXXX................. 16
    data_0_cmp_eq0001/data_0_cmp_eq0001_D2
                         .......XXXXXXXXXXXXXXXX................. 16
    centronics_data      X.XX.X..XXXXXXXXXXXXXXX.X....XXXXXX..... 26
    centronics_strobe    .X.XX..X.XX..............X...XXXXX...... 12
    data_0_cmp_eq0000/data_0_cmp_eq0000_D2
                         .......XXXXXXXXXXXXXXXX................. 16
    centronics_clk       X.XX..XXXXXXXX.XXXXXXXXX.....XXXXXX..... 26
    summer               .......X...XXXX..............XXXXXX..... 11
    $OpTx$FX_DC$640      X......XXXXXXXXXXXXXXXX........XX....... 19
    density_out<2>       ............................X........... 1
    density_out<1>       ...........................X............ 1
    $OpTx$FX_DC$624      ........XXXXXXXXXXXXXXX...........X..... 16
    density_out<0>       ..........................X............. 1
    track_hi_out<6>      ...................................X.... 1
    $OpTx$FX_DC$555      .......XXXXXXXXXXXXXXXX................. 16
    $OpTx$INV$547        X.......XXXXXX.XXXXXXXX......XXXX.X..... 20
    $OpTx$INV$548        .......XXXXXXXXXXXXXXXX................. 16
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *******************************  Equations  ********************************

    ********** Mapped Logic **********

    $OpTx$FX_DC$551 <= NOT (floppy_mode(0)
    	 XOR
    $OpTx$FX_DC$551 <= NOT (floppy_mode(1));

    $OpTx$FX_DC$555 <= (adr(12) AND NOT adr(6) AND NOT adr(3) AND adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    $OpTx$FX_DC$571 <= ((NOT floppy_mode(2) AND NOT adr(13))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1)));

    $OpTx$FX_DC$601 <= ((NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(0) AND
    	NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1)));

    $OpTx$FX_DC$602 <= ((adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(11))
    	OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(10) AND adr(11))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND
    	NOT adr(14) AND adr(15))
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1) AND NOT rw)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND NOT adr(14) AND adr(15)));

    $OpTx$FX_DC$617 <= ((NOT ram_ce)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(11))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15) AND $OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND adr(14) AND rw AND adr(15))
    	OR (NOT floppy_mode(2) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15))
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT rom_source_is_ram AND rw)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)));

    $OpTx$FX_DC$624 <= (adr(12) AND NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND
    	NOT rw AND NOT adr(15) AND adr(5) AND NOT adr(1) AND adr(4) AND adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    $OpTx$FX_DC$640 <= (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT adr(6) AND adr(3) AND adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND
    	NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND NOT adr(10) AND NOT adr(9) AND
    	NOT adr(11) AND NOT adr(8) AND NOT adr(7) AND $OpTx$FX_DC$551);

    $OpTx$INV$546 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15))
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15))
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)));

    $OpTx$INV$547 <= ((adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(11))
    	OR (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND
    	adr(5) AND adr(4) AND NOT adr(2) AND NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND
    	NOT adr(8) AND NOT adr(7) AND $OpTx$FX_DC$551));

    $OpTx$INV$548 <= ((adr(12) AND adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND
    	NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND NOT adr(10) AND
    	NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7))
    	OR (adr(12) AND adr(6) AND NOT adr(0) AND adr(13) AND adr(14) AND
    	NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND NOT adr(10) AND
    	NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7))
    	OR (adr(12) AND NOT adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND NOT adr(10) AND
    	NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7))
    	OR (adr(12) AND NOT adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND NOT adr(10) AND
    	NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7))
    	OR (adr(12) AND NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND
    	NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND NOT adr(10) AND
    	NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7)));

    N11/N11_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1))
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(0) AND
    	NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)));

    N120/N120_D2 <= (NOT adr(10) AND NOT adr(9) AND NOT adr(7) AND
    	check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2);

    N2/N2_D2 <= ((NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND
    	NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)));

    N76/N76_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND $OpTx$FX_DC$551));

    FDCPE_centronics_clk: FDCPE port map (centronics_clk,centronics_clk_D,NOT phi2,'0','0');
    centronics_clk_D <= ((NOT reset)
    	OR (centronics_clk AND NOT $OpTx$INV$547)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND d7_ram_rom.PIN AND data(4).PIN AND
    	NOT adr(11))
    	OR (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT adr(6) AND NOT adr(3) AND adr(0) AND adr(13) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND adr(5) AND adr(4) AND NOT adr(2) AND NOT adr(10) AND NOT adr(9) AND
    	NOT adr(11) AND NOT adr(8) AND NOT adr(7) AND $OpTx$FX_DC$551));

    FDCPE_centronics_data: FDCPE port map (centronics_data,centronics_data_D,NOT phi2,'0','0');
    centronics_data_D <= ((NOT reset)
    	OR (centronics_data AND NOT $OpTx$INV$547)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND data(5).PIN AND d7_ram_rom.PIN AND
    	NOT adr(11))
    	OR (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND
    	adr(5) AND adr(1) AND adr(4) AND NOT adr(2) AND NOT adr(10) AND NOT adr(9) AND
    	NOT adr(11) AND NOT adr(8) AND NOT adr(7) AND $OpTx$FX_DC$551));

    FTCPE_centronics_strobe: FTCPE port map (centronics_strobe,centronics_strobe_T,NOT phi2,'0','0');
    centronics_strobe_T <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	floppy_mode(1) AND NOT adr(0) AND centronics_strobe AND reset AND
    	$OpTx$FX_DC$624)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	NOT floppy_mode(1) AND NOT adr(0) AND centronics_strobe AND reset AND
    	$OpTx$FX_DC$624)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND d7_ram_rom.PIN AND NOT adr(11) AND
    	centronics_strobe AND reset AND NOT data(6).PIN)
    	OR (NOT centronics_strobe AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	floppy_mode(1) AND adr(0) AND NOT centronics_strobe AND $OpTx$FX_DC$624)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	NOT floppy_mode(1) AND adr(0) AND NOT centronics_strobe AND $OpTx$FX_DC$624)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT d7_ram_rom.PIN AND NOT adr(11) AND
    	NOT centronics_strobe)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(11) AND NOT centronics_strobe AND
    	data(6).PIN));

    FDCPE_cfg_led: FDCPE port map (cfg_led,cfg_led_D,NOT phi2,'0','0');
    cfg_led_D <= ((data(0).PIN AND reset AND $OpTx$FX_DC$640)
    	OR (cfg_led AND reset AND NOT $OpTx$FX_DC$640));

    check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 <= ((NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	NOT adr(14) AND NOT adr(15))
    	OR (NOT floppy_mode(2) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	NOT adr(13) AND NOT adr(14) AND NOT adr(15))
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	NOT floppy_mode(1))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	NOT adr(15)));

    d7_ram_rom_I <= data(7).PIN;
    d7_ram_rom <= d7_ram_rom_I when d7_ram_rom_OE = '1' else 'Z';
    d7_ram_rom_OE <= (phi2 AND NOT rw AND $OpTx$FX_DC$617);

    data_I(0) <= ((ms_speed_select AND NOT $OpTx$FX_DC$555 AND
    	data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (ms_write_enable AND NOT $OpTx$FX_DC$555 AND
    	data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND
    	NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND
    	NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (turbo_speed_in AND NOT $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND
    	NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND
    	NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (cfg_enc_a AND
    	data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_bank_c000_0 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_base_bank_0 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (floppy_mode(0) AND $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2));
    data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
    data_OE(0) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(1) <= ((archiver_a11 AND NOT $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND
    	NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND
    	NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (cfg_enc_b AND
    	data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_bank_c000_1 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_base_bank_1 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (floppy_mode(1) AND $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2));
    data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
    data_OE(1) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(2) <= ((floppy_mode(2) AND $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (riot_ready_in AND NOT $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND
    	NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND
    	NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (cfg_enc_ok AND
    	data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_bank_c000_enable(0) AND rom_bank_c000_2 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_3 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_base_bank_2 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2));
    data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
    data_OE(2) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(3) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_3 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (floppy_mode(3) AND $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (fdc_write_in AND NOT $OpTx$FX_DC$555 AND
    	NOT data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND
    	NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND
    	NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (cfg_sw1 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_4 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_base_bank_3 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2));
    data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
    data_OE(3) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(4) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_4 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_5 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_base_bank_4 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2)
    	OR (cfg_sw2 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2));
    data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
    data_OE(4) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(5) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_5 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_6 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)
    	OR (rom_base_bank_5 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2));
    data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
    data_OE(5) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(6) <= (rom_base_bank_6 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2);
    data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
    data_OE(6) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548);

    data_I(7) <= ((floppy_mode(2) AND NOT floppy_mode(0) AND d7_ram_rom.PIN)
    	OR (floppy_mode(2) AND floppy_mode(1) AND d7_ram_rom.PIN)
    	OR (NOT floppy_mode(2) AND d7_ram_rom.PIN AND
    	NOT $OpTx$FX_DC$551)
    	OR ($OpTx$FX_DC$617.EXP)
    	OR (NOT floppy_mode(2) AND d7_ram_rom.PIN AND NOT $OpTx$INV$548 AND
    	NOT i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	i2c_data_pin.PIN AND $OpTx$FX_DC$551 AND
    	NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT rom_bank_c000_enable(0) AND $OpTx$FX_DC$551 AND
    	data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	NOT i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND rw AND NOT adr(11) AND centronics_busy)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_source_is_ram AND $OpTx$FX_DC$551 AND
    	NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND
    	data_0_cmp_eq0002/data_0_cmp_eq0002_D2 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (floppy_mode(3) AND d7_ram_rom.PIN)
    	OR (NOT adr(12) AND floppy_mode(2) AND d7_ram_rom.PIN)
    	OR (floppy_mode(2) AND NOT rw AND d7_ram_rom.PIN)
    	OR (floppy_mode(2) AND d7_ram_rom.PIN AND adr(11)));
    data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
    data_OE(7) <= data_7_mux0000/data_7_mux0000_TRST;

    data_0_cmp_eq0000/data_0_cmp_eq0000_D2 <= (adr(12) AND NOT adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    data_0_cmp_eq0001/data_0_cmp_eq0001_D2 <= (adr(12) AND NOT adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    data_0_cmp_eq0002/data_0_cmp_eq0002_D2 <= (adr(12) AND NOT adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    data_0_cmp_eq0004/data_0_cmp_eq0004_D2 <= (adr(12) AND NOT adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    data_0_cmp_eq0005/data_0_cmp_eq0005_D2 <= (adr(12) AND adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    data_0_cmp_eq0006/data_0_cmp_eq0006_D2 <= (adr(12) AND adr(6) AND NOT adr(3) AND adr(0) AND adr(13) AND
    	adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND
    	NOT adr(10) AND NOT adr(9) AND NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    data_7_mux0000/data_7_mux0000_TRST <= ((phi2 AND rw AND $OpTx$FX_DC$617)
    	OR (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND $OpTx$INV$548)
    	OR (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND
    	$OpTx$FX_DC$551 AND i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (adr(12) AND phi2 AND NOT floppy_mode(3) AND
    	floppy_mode(2) AND floppy_mode(0) AND NOT floppy_mode(1) AND rw AND NOT adr(11)));

    FDCPE_density0: FDCPE port map (density(0),density_D(0),NOT phi2,'0','0');
    density_D(0) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(6).PIN)
    	OR (density(0) AND NOT $OpTx$FX_DC$601)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(7).PIN)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$571));

    FDCPE_density1: FDCPE port map (density(1),density_D(1),NOT phi2,'0','0');
    density_D(1) <= ((NOT reset)
    	OR (density(1) AND NOT $OpTx$FX_DC$601)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(7).PIN)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND adr(1) AND NOT data(1).PIN AND $OpTx$FX_DC$571));

    FDCPE_density2: FDCPE port map (density(2),density_D(2),NOT phi2,'0','0');
    density_D(2) <= ((NOT reset)
    	OR (density(2) AND NOT $OpTx$FX_DC$601)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(6).PIN)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND adr(1) AND NOT data(2).PIN AND $OpTx$FX_DC$571));

    density_out_I(0) <= '0';
    density_out(0) <= density_out_I(0) when density_out_OE(0) = '1' else 'Z';
    density_out_OE(0) <= NOT density(0);

    density_out_I(1) <= '0';
    density_out(1) <= density_out_I(1) when density_out_OE(1) = '1' else 'Z';
    density_out_OE(1) <= NOT density(1);

    density_out_I(2) <= '0';
    density_out(2) <= density_out_I(2) when density_out_OE(2) = '1' else 'Z';
    density_out_OE(2) <= NOT density(2);

    fdc_write_out <= NOT (((NOT fdc_write_in)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT ms_write_enable AND $OpTx$FX_DC$551)
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND
    	NOT archiver_a11 AND $OpTx$FX_DC$551)));

    FTCPE_floppy_mode0: FTCPE port map (floppy_mode(0),floppy_mode_T(0),NOT phi2,'0','0');
    floppy_mode_T(0) <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	data(0).PIN AND reset AND $OpTx$FX_DC$551 AND $OpTx$FX_DC$555)
    	OR (floppy_mode(0) AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT data(0).PIN AND $OpTx$FX_DC$551 AND $OpTx$FX_DC$555));

    FTCPE_floppy_mode1: FTCPE port map (floppy_mode(1),floppy_mode_T(1),NOT phi2,'0','0');
    floppy_mode_T(1) <= ((floppy_mode(1) AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND
    	NOT data(1).PIN AND $OpTx$FX_DC$551 AND $OpTx$FX_DC$555)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND
    	data(1).PIN AND reset AND $OpTx$FX_DC$551 AND $OpTx$FX_DC$555));

    FDCPE_floppy_mode2: FDCPE port map (floppy_mode(2),floppy_mode_D(2),NOT phi2,'0','0');
    floppy_mode_D(2) <= ((floppy_mode(2) AND reset)
    	OR (NOT floppy_mode(3) AND data(2).PIN AND reset AND
    	$OpTx$FX_DC$551 AND $OpTx$FX_DC$555));

    FDCPE_floppy_mode3: FDCPE port map (floppy_mode(3),floppy_mode_D(3),NOT phi2,'0','0');
    floppy_mode_D(3) <= ((floppy_mode(3) AND reset)
    	OR (NOT floppy_mode(2) AND data(3).PIN AND reset AND
    	$OpTx$FX_DC$551 AND $OpTx$FX_DC$555));

    FTCPE_happy_a12: FTCPE port map (happy_a12,happy_a12_T,NOT phi2,'0','0');
    happy_a12_T <= ((NOT happy_a12 AND NOT reset AND
    	happy_a12__or0001/happy_a12__or0001_D2)
    	OR (adr(3) AND adr(0) AND NOT adr(1) AND NOT happy_a12 AND NOT adr(2) AND
    	happy_a12__or0001/happy_a12__or0001_D2)
    	OR (adr(3) AND NOT adr(0) AND NOT adr(1) AND happy_a12 AND NOT adr(2) AND
    	reset AND happy_a12__or0001/happy_a12__or0001_D2));

    happy_a12__or0001/happy_a12__or0001_D2 <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(6) AND adr(14) AND adr(15) AND adr(5) AND adr(4) AND
    	adr(10) AND adr(9) AND adr(11) AND adr(8) AND adr(7)));

    FTCPE_i2c_clk: FTCPE port map (i2c_clk,i2c_clk_T,NOT phi2,'0','0');
    i2c_clk_T <= ((NOT i2c_clk AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND NOT rw AND
    	NOT i2c_clk AND $OpTx$FX_DC$551 AND
    	i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(0) AND NOT rw AND
    	i2c_clk AND reset AND $OpTx$FX_DC$551 AND
    	i2c_clk_and0000/i2c_clk_and0000_D2));

    i2c_clk_and0000/i2c_clk_and0000_D2 <= (adr(12) AND NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND
    	NOT adr(15) AND adr(5) AND NOT adr(4) AND NOT adr(2) AND NOT adr(10) AND NOT adr(9) AND
    	NOT adr(11) AND NOT adr(8) AND NOT adr(7));

    i2c_clk_pin_I <= '0';
    i2c_clk_pin <= i2c_clk_pin_I when i2c_clk_pin_OE = '1' else 'Z';
    i2c_clk_pin_OE <= NOT i2c_clk;

    FTCPE_i2c_data: FTCPE port map (i2c_data,i2c_data_T,NOT phi2,'0','0');
    i2c_data_T <= ((NOT i2c_data AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND adr(1) AND
    	NOT i2c_data AND $OpTx$FX_DC$551 AND
    	i2c_clk_and0000/i2c_clk_and0000_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND NOT adr(1) AND
    	i2c_data AND reset AND $OpTx$FX_DC$551 AND
    	i2c_clk_and0000/i2c_clk_and0000_D2));

    i2c_data_pin_I <= '0';
    i2c_data_pin <= i2c_data_pin_I when i2c_data_pin_OE = '1' else 'Z';
    i2c_data_pin_OE <= NOT i2c_data;

    io_1050 <= NOT (((NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND adr(7))
    	OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(11) AND adr(7))
    	OR (adr(10) AND
    	check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2)
    	OR (adr(9) AND
    	check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2)
    	OR (adr(7) AND
    	check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2)
    	OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND adr(10))
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND adr(10))));

    FTCPE_ms_speed_select: FTCPE port map (ms_speed_select,ms_speed_select_T,NOT phi2,'0','0');
    ms_speed_select_T <= ((NOT ms_speed_select AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND
    	NOT ms_speed_select AND data(0).PIN AND $OpTx$FX_DC$551 AND
    	data_0_cmp_eq0005/data_0_cmp_eq0005_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND
    	ms_speed_select AND NOT data(0).PIN AND reset AND $OpTx$FX_DC$551 AND
    	data_0_cmp_eq0005/data_0_cmp_eq0005_D2));

    FTCPE_ms_write_enable: FTCPE port map (ms_write_enable,ms_write_enable_T,NOT phi2,'0','0');
    ms_write_enable_T <= ((NOT ms_write_enable AND NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND
    	NOT ms_write_enable AND data(0).PIN AND $OpTx$FX_DC$551 AND
    	data_0_cmp_eq0006/data_0_cmp_eq0006_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND
    	ms_write_enable AND NOT data(0).PIN AND reset AND $OpTx$FX_DC$551 AND
    	data_0_cmp_eq0006/data_0_cmp_eq0006_D2));

    FDCPE_ram_bank_0: FDCPE port map (ram_bank_0,ram_bank_0_D,NOT phi2,'0','0');
    ram_bank_0_D <= ((reset AND ram_bank_0 AND NOT $OpTx$INV$546)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(0).PIN AND reset AND
    	$OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(0).PIN AND
    	reset));

    FDCPE_ram_bank_1: FDCPE port map (ram_bank_1,ram_bank_1_D,NOT phi2,'0','0');
    ram_bank_1_D <= ((reset AND ram_bank_1 AND NOT $OpTx$INV$546)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND reset AND
    	$OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	reset));

    FDCPE_ram_bank_2: FDCPE port map (ram_bank_2,ram_bank_2_D,NOT phi2,'0','0');
    ram_bank_2_D <= ((reset AND ram_bank_2 AND NOT $OpTx$INV$546)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(2).PIN AND reset AND
    	$OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(2).PIN AND
    	reset));

    FDCPE_ram_bank_3: FDCPE port map (ram_bank_3,ram_bank_3_D,NOT phi2,'0','0');
    ram_bank_3_D <= ((reset AND ram_bank_3 AND NOT $OpTx$INV$546)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND reset AND
    	$OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND
    	reset));

    FDCPE_ram_bank_4: FDCPE port map (ram_bank_4,ram_bank_4_D,NOT phi2,'0','0');
    ram_bank_4_D <= ((reset AND ram_bank_4 AND NOT $OpTx$INV$546)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN AND reset AND
    	$OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN AND
    	reset));

    FDCPE_ram_bank_5: FDCPE port map (ram_bank_5,ram_bank_5_D,NOT phi2,'0','0');
    ram_bank_5_D <= ((NOT adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND reset AND
    	$OpTx$FX_DC$551)
    	OR (reset AND ram_bank_5 AND NOT $OpTx$INV$546));

    ram_ce <= NOT (((N120/N120_D2)
    	OR ($OpTx$FX_DC$602)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND rom_source_is_ram AND rw)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND
    	NOT adr(14) AND adr(15) AND NOT ram_bank_3)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND
    	NOT adr(14) AND adr(15) AND NOT ram_bank_4)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT rom_bank_c000_enable(0) AND rom_source_is_ram AND adr(14) AND rw AND adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15))
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(10) AND NOT adr(7))
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	rom_source_is_ram AND adr(14) AND rw AND adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND rom_source_is_ram AND adr(14) AND rw AND adr(15))
    	OR (NOT floppy_mode(2) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	adr(15) AND $OpTx$FX_DC$551)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(1) AND rom_source_is_ram AND rw)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	NOT floppy_mode(1) AND rom_source_is_ram AND rw)));

    ram_rom_adr(8) <= ((adr(10) AND adr(8) AND NOT N120/N120_D2)
    	OR (adr(8) AND adr(7) AND NOT N120/N120_D2)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(10) AND adr(9) AND NOT adr(7) AND
    	NOT N120/N120_D2)
    	OR (adr(12) AND adr(8) AND NOT N120/N120_D2)
    	OR (floppy_mode(3) AND adr(8) AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(2) AND adr(8) AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(0) AND adr(8) AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(1) AND adr(8) AND NOT N120/N120_D2));

    ram_rom_adr(9) <= ((adr(9))
    	OR (N120/N120_D2)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(10) AND NOT adr(7)));

    ram_rom_adr(10) <= ((adr(10))
    	OR (N120/N120_D2)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(7)));

    ram_rom_adr(11) <= NOT (((track_hi(6).EXP)
    	OR (NOT floppy_mode(0) AND NOT adr(11) AND NOT N120/N120_D2)
    	OR (NOT adr(12) AND NOT adr(11) AND adr(7) AND NOT N120/N120_D2)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1) AND NOT rw AND NOT N120/N120_D2)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1) AND NOT archiver_a11 AND NOT N120/N120_D2)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT turbo_rom_adr(11) AND
    	NOT N120/N120_D2)
    	OR (floppy_mode(3) AND NOT adr(11) AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(2) AND NOT adr(11) AND NOT N120/N120_D2)
    	OR (NOT adr(12) AND NOT floppy_mode(1) AND NOT adr(11) AND
    	NOT N120/N120_D2)
    	OR (NOT adr(12) AND adr(10) AND NOT adr(11) AND NOT N120/N120_D2)
    	OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(10) AND NOT N120/N120_D2)));

    ram_rom_adr(12) <= ((N120/N120_D2)
    	OR (EXP20_.EXP)
    	OR (floppy_mode(3) AND floppy_mode(0) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND rom_base_bank_0)
    	OR (floppy_mode(3) AND floppy_mode(0) AND
    	NOT rom_source_is_ram AND rom_base_bank_0 AND NOT adr(11))
    	OR (floppy_mode(2) AND floppy_mode(0) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND rom_base_bank_0)
    	OR (floppy_mode(2) AND NOT floppy_mode(0) AND NOT floppy_mode(1) AND
    	NOT rom_source_is_ram AND rom_base_bank_0)
    	OR (floppy_mode(2) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_0)
    	OR ($OpTx$FX_DC$602.EXP)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND turbo_rom_adr(12))
    	OR (floppy_mode(3) AND floppy_mode(0) AND
    	NOT rom_source_is_ram AND rom_base_bank_0 AND adr(10))
    	OR (floppy_mode(3) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND NOT adr(13) AND rom_base_bank_0)
    	OR (adr(12) AND floppy_mode(3) AND NOT rom_source_is_ram AND
    	rw AND rom_base_bank_0 AND adr(11))
    	OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(0) AND
    	NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0)
    	OR (adr(12) AND NOT floppy_mode(3) AND NOT floppy_mode(2))
    	OR (floppy_mode(3) AND floppy_mode(2) AND
    	NOT rom_source_is_ram AND rom_base_bank_0)
    	OR (adr(12) AND floppy_mode(3) AND floppy_mode(0) AND
    	NOT rom_source_is_ram AND rom_base_bank_0)
    	OR (NOT adr(12) AND floppy_mode(2) AND NOT floppy_mode(1) AND
    	NOT rom_source_is_ram AND rom_base_bank_0));

    ram_rom_adr(13) <= ((adr(12) AND floppy_mode(2) AND NOT rom_source_is_ram AND
    	rom_base_bank_1 AND NOT N120/N120_D2)
    	OR (floppy_mode(2) AND NOT floppy_mode(1) AND
    	NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N120/N120_D2)
    	OR (floppy_mode(2) AND NOT rom_source_is_ram AND
    	rom_base_bank_1 AND adr(10) AND NOT N120/N120_D2)
    	OR (floppy_mode(2) AND NOT rom_source_is_ram AND
    	rom_base_bank_1 AND adr(7) AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	adr(15) AND ram_bank_0 AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(14) AND
    	adr(15) AND rom_bank_c000_0 AND $OpTx$FX_DC$551 AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(2) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	adr(13) AND NOT adr(14) AND NOT adr(15) AND NOT N120/N120_D2)
    	OR (NOT N120/N120_D2 AND $OpTx$FX_DC$602)
    	OR (floppy_mode(3) AND NOT rom_source_is_ram AND
    	rom_base_bank_1 AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND
    	adr(14) AND NOT N120/N120_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND
    	NOT adr(15) AND NOT N120/N120_D2)
    	OR (floppy_mode(2) AND NOT floppy_mode(0) AND
    	NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N120/N120_D2));

    ram_rom_adr(14) <= ((N120/N120_D2)
    	OR ($OpTx$FX_DC$602)
    	OR (EXP16_.EXP)
    	OR (floppy_mode(3) AND NOT rom_source_is_ram AND
    	rom_base_bank_2)
    	OR (floppy_mode(2) AND NOT rom_source_is_ram AND
    	rom_base_bank_2)
    	OR (NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(15) AND
    	$OpTx$FX_DC$551)
    	OR (NOT rom_source_is_ram AND adr(14) AND rom_base_bank_2 AND
    	NOT $OpTx$FX_DC$551));

    ram_rom_adr(15) <= NOT (((N120/N120_D2)
    	OR (NOT rom_bank_c000_enable(0) AND NOT rom_source_is_ram AND
    	adr(14) AND NOT rom_base_bank_3)
    	OR (NOT rom_source_is_ram AND adr(14) AND NOT rom_base_bank_3 AND
    	NOT $OpTx$FX_DC$551)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND
    	NOT adr(14) AND adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	adr(15) AND NOT ram_bank_2)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND NOT adr(14) AND adr(15))
    	OR (track_lo(0).EXP)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1) AND NOT rw)
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(11))
    	OR (NOT adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT adr(10) AND adr(11))
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(10) AND NOT adr(7))
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15))
    	OR (floppy_mode(3) AND NOT rom_source_is_ram AND
    	NOT rom_base_bank_3)
    	OR (floppy_mode(2) AND NOT rom_source_is_ram AND
    	NOT rom_base_bank_3)
    	OR (NOT rom_source_is_ram AND NOT adr(15) AND NOT rom_base_bank_3)
    	OR (NOT rom_source_is_ram AND adr(13) AND adr(14) AND
    	NOT rom_base_bank_3)));

    ram_rom_adr(16) <= ((N120/N120_D2)
    	OR ($OpTx$FX_DC$602)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(10) AND NOT adr(7))
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_3 AND
    	$OpTx$FX_DC$551)
    	OR (rom_source_is_ram AND NOT N76/N76_D2)
    	OR (rom_base_bank_4 AND NOT N76/N76_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	adr(15) AND ram_bank_3));

    ram_rom_adr(17) <= ((N120/N120_D2)
    	OR ($OpTx$FX_DC$602)
    	OR (ram_rom_adr_18_OBUF.EXP)
    	OR (rom_source_is_ram AND NOT N76/N76_D2)
    	OR (rom_base_bank_5 AND NOT N76/N76_D2)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND
    	adr(15) AND ram_bank_4)
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_4 AND
    	$OpTx$FX_DC$551));

    ram_rom_adr(18) <= ((N120/N120_D2)
    	OR ($OpTx$FX_DC$602)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT adr(14) AND adr(15) AND ram_bank_5)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND
    	NOT adr(14) AND adr(15) AND ram_bank_5)
    	OR (NOT adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND floppy_mode(1) AND NOT adr(10) AND NOT adr(7))
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(13) AND NOT adr(14) AND NOT adr(15))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_5 AND
    	$OpTx$FX_DC$551)
    	OR (rom_source_is_ram AND NOT N76/N76_D2)
    	OR (rom_base_bank_6 AND NOT N76/N76_D2));

    ram_rom_oe <= NOT ((phi2 AND rw));

    ram_rom_we <= NOT ((phi2 AND NOT rw));

    FDCPE_reset: FDCPE port map (reset,reset_sync,NOT phi2,'0','0');

    FDCPE_reset_sync: FDCPE port map (reset_sync,reset_in,NOT phi2,'0','0');

    riot_ready_inout_I <= riot_ready_in;
    riot_ready_inout <= riot_ready_inout_I when riot_ready_inout_OE = '1' else 'Z';
    riot_ready_inout_OE <= NOT ((floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	NOT floppy_mode(1)));

    FDCPE_rom_bank_c000_0: FDCPE port map (rom_bank_c000_0,rom_bank_c000_0_D,NOT phi2,'0','0');
    rom_bank_c000_0_D <= ((rom_bank_c000_0 AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (data(0).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND
    	$OpTx$FX_DC$551 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2));

    FDCPE_rom_bank_c000_1: FDCPE port map (rom_bank_c000_1,rom_bank_c000_1_D,NOT phi2,'0','0');
    rom_bank_c000_1_D <= ((NOT rom_bank_c000_1 AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (NOT data(1).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    FDCPE_rom_bank_c000_2: FDCPE port map (rom_bank_c000_2,rom_bank_c000_2_D,NOT phi2,'0','0');
    rom_bank_c000_2_D <= ((rom_bank_c000_2 AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (data(2).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    FDCPE_rom_bank_c000_3: FDCPE port map (rom_bank_c000_3,rom_bank_c000_3_D,NOT phi2,'0','0');
    rom_bank_c000_3_D <= ((rom_bank_c000_3 AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (data(3).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    FDCPE_rom_bank_c000_4: FDCPE port map (rom_bank_c000_4,rom_bank_c000_4_D,NOT phi2,'0','0');
    rom_bank_c000_4_D <= ((rom_bank_c000_4 AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (data(4).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    FDCPE_rom_bank_c000_5: FDCPE port map (rom_bank_c000_5,rom_bank_c000_5_D,NOT phi2,'0','0');
    rom_bank_c000_5_D <= ((rom_bank_c000_5 AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (data(5).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    FDCPE_rom_bank_c000_enable0: FDCPE port map (rom_bank_c000_enable(0),rom_bank_c000_enable_D(0),NOT phi2,'0','0');
    rom_bank_c000_enable_D(0) <= ((rom_bank_c000_enable(0) AND
    	NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)
    	OR (NOT data(7).PIN AND reset AND
    	rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2));

    FDCPE_rom_base_bank_0: FDCPE port map (rom_base_bank_0,rom_base_bank_0_D,NOT phi2,'0','0');
    rom_base_bank_0_D <= ((rom_base_bank_0 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (data(0).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	$OpTx$FX_DC$551 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2));

    FDCPE_rom_base_bank_1: FDCPE port map (rom_base_bank_1,rom_base_bank_1_D,NOT phi2,'0','0');
    rom_base_bank_1_D <= ((rom_base_bank_1 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (data(1).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    FDCPE_rom_base_bank_2: FDCPE port map (rom_base_bank_2,rom_base_bank_2_D,NOT phi2,'0','0');
    rom_base_bank_2_D <= ((rom_base_bank_2 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (data(2).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    FDCPE_rom_base_bank_3: FDCPE port map (rom_base_bank_3,rom_base_bank_3_D,NOT phi2,'0','0');
    rom_base_bank_3_D <= ((NOT rom_base_bank_3 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (NOT data(3).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    FDCPE_rom_base_bank_4: FDCPE port map (rom_base_bank_4,rom_base_bank_4_D,NOT phi2,'0','0');
    rom_base_bank_4_D <= ((NOT rom_base_bank_4 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (NOT data(4).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    FDCPE_rom_base_bank_5: FDCPE port map (rom_base_bank_5,rom_base_bank_5_D,NOT phi2,'0','0');
    rom_base_bank_5_D <= ((NOT rom_base_bank_5 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (NOT data(5).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    FDCPE_rom_base_bank_6: FDCPE port map (rom_base_bank_6,rom_base_bank_6_D,NOT phi2,'0','0');
    rom_base_bank_6_D <= ((NOT rom_base_bank_6 AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (reset AND NOT data(6).PIN AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    rom_ce <= NOT (((adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND adr(14) AND rw AND adr(15))
    	OR (NOT floppy_mode(2) AND NOT floppy_mode(0) AND floppy_mode(1) AND
    	NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15))
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT rom_source_is_ram AND rw)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT rom_source_is_ram AND adr(14) AND rw AND adr(15))
    	OR (adr(12) AND floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(11))
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15) AND $OpTx$FX_DC$551)));

    FDCPE_rom_source_is_ram: FDCPE port map (rom_source_is_ram,rom_source_is_ram_D,NOT phi2,'0','0');
    rom_source_is_ram_D <= ((rom_source_is_ram AND
    	NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)
    	OR (data(7).PIN AND reset AND
    	rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2));

    FTCPE_summer: FTCPE port map (summer,summer_T,NOT phi2,'0','0');
    summer_T <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND
    	NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset)
    	OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND
    	reset));

    FDCPE_track_hi0: FDCPE port map (track_hi(0),track_hi_D(0),NOT phi2,'0','0');
    track_hi_D(0) <= ((NOT reset)
    	OR (track_hi(0) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND
    	data(4).PIN));

    FDCPE_track_hi1: FDCPE port map (track_hi(1),track_hi_D(1),NOT phi2,'0','0');
    track_hi_D(1) <= ((NOT reset)
    	OR (track_hi(1) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(1).PIN AND $OpTx$FX_DC$571));

    FDCPE_track_hi2: FDCPE port map (track_hi(2),track_hi_D(2),NOT phi2,'0','0');
    track_hi_D(2) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND
    	NOT data(4).PIN)
    	OR (track_hi(2) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(2).PIN AND $OpTx$FX_DC$571));

    FDCPE_track_hi3: FDCPE port map (track_hi(3),track_hi_D(3),NOT phi2,'0','0');
    track_hi_D(3) <= ((NOT reset)
    	OR (track_hi(3) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(3).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND
    	data(4).PIN));

    FDCPE_track_hi4: FDCPE port map (track_hi(4),track_hi_D(4),NOT phi2,'0','0');
    track_hi_D(4) <= ((NOT reset)
    	OR (track_hi(4) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$571));

    FDCPE_track_hi5: FDCPE port map (track_hi(5),track_hi_D(5),NOT phi2,'0','0');
    track_hi_D(5) <= ((NOT reset)
    	OR (track_hi(5) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$571));

    FDCPE_track_hi6: FDCPE port map (track_hi(6),track_hi_D(6),NOT phi2,'0','0');
    track_hi_D(6) <= ((NOT reset)
    	OR (track_hi(6) AND NOT N2/N2_D2)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN)
    	OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$571));

    track_hi_out_I(0) <= '0';
    track_hi_out(0) <= track_hi_out_I(0) when track_hi_out_OE(0) = '1' else 'Z';
    track_hi_out_OE(0) <= NOT track_hi(0);

    track_hi_out_I(1) <= '0';
    track_hi_out(1) <= track_hi_out_I(1) when track_hi_out_OE(1) = '1' else 'Z';
    track_hi_out_OE(1) <= NOT track_hi(1);

    track_hi_out_I(2) <= '0';
    track_hi_out(2) <= track_hi_out_I(2) when track_hi_out_OE(2) = '1' else 'Z';
    track_hi_out_OE(2) <= NOT track_hi(2);

    track_hi_out_I(3) <= '0';
    track_hi_out(3) <= track_hi_out_I(3) when track_hi_out_OE(3) = '1' else 'Z';
    track_hi_out_OE(3) <= NOT track_hi(3);

    track_hi_out_I(4) <= '0';
    track_hi_out(4) <= track_hi_out_I(4) when track_hi_out_OE(4) = '1' else 'Z';
    track_hi_out_OE(4) <= NOT track_hi(4);

    track_hi_out_I(5) <= '0';
    track_hi_out(5) <= track_hi_out_I(5) when track_hi_out_OE(5) = '1' else 'Z';
    track_hi_out_OE(5) <= NOT track_hi(5);

    track_hi_out_I(6) <= '0';
    track_hi_out(6) <= track_hi_out_I(6) when track_hi_out_OE(6) = '1' else 'Z';
    track_hi_out_OE(6) <= NOT track_hi(6);

    FDCPE_track_lo0: FDCPE port map (track_lo(0),track_lo_D(0),NOT phi2,'0','0');
    track_lo_D(0) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	data(3).PIN AND data(2).PIN AND data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN)
    	OR (track_lo(0) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	data(3).PIN AND NOT data(2).PIN AND data(0).PIN));

    FDCPE_track_lo1: FDCPE port map (track_lo(1),track_lo_D(1),NOT phi2,'0','0');
    track_lo_D(1) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	data(3).PIN AND data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	data(2).PIN AND NOT data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND
    	data(2).PIN AND NOT data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND data(2).PIN AND data(0).PIN)
    	OR (track_lo(1) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(1).PIN AND $OpTx$FX_DC$571));

    FDCPE_track_lo2: FDCPE port map (track_lo(2),track_lo_D(2),NOT phi2,'0','0');
    track_lo_D(2) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	data(3).PIN AND data(2).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND
    	data(2).PIN AND NOT data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	NOT data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN)
    	OR (track_lo(2) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(2).PIN AND $OpTx$FX_DC$571));

    FDCPE_track_lo3: FDCPE port map (track_lo(3),track_lo_D(3),NOT phi2,'0','0');
    track_lo_D(3) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN)
    	OR (track_lo(3) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(3).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	data(2).PIN AND data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN));

    FDCPE_track_lo4: FDCPE port map (track_lo(4),track_lo_D(4),NOT phi2,'0','0');
    track_lo_D(4) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(2).PIN AND data(0).PIN)
    	OR (track_lo(4) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND
    	data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND data(2).PIN));

    FDCPE_track_lo5: FDCPE port map (track_lo(5),track_lo_D(5),NOT phi2,'0','0');
    track_lo_D(5) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND
    	NOT data(2).PIN AND data(0).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	data(3).PIN AND data(2).PIN AND data(0).PIN)
    	OR (track_lo(5) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	NOT data(3).PIN AND NOT data(2).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	NOT data(3).PIN AND data(0).PIN));

    FDCPE_track_lo6: FDCPE port map (track_lo(6),track_lo_D(6),NOT phi2,'0','0');
    track_lo_D(6) <= ((NOT reset)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	data(3).PIN AND data(2).PIN AND NOT data(0).PIN)
    	OR (track_lo(6) AND NOT N11/N11_D2)
    	OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND
    	NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$571)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND
    	NOT data(3).PIN AND NOT data(2).PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(0) AND
    	floppy_mode(1) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND
    	NOT data(3).PIN AND data(2).PIN AND data(0).PIN));

    track_lo_out_I(0) <= '0';
    track_lo_out(0) <= track_lo_out_I(0) when track_lo_out_OE(0) = '1' else 'Z';
    track_lo_out_OE(0) <= NOT track_lo(0);

    track_lo_out_I(1) <= '0';
    track_lo_out(1) <= track_lo_out_I(1) when track_lo_out_OE(1) = '1' else 'Z';
    track_lo_out_OE(1) <= NOT track_lo(1);

    track_lo_out_I(2) <= '0';
    track_lo_out(2) <= track_lo_out_I(2) when track_lo_out_OE(2) = '1' else 'Z';
    track_lo_out_OE(2) <= NOT track_lo(2);

    track_lo_out_I(3) <= '0';
    track_lo_out(3) <= track_lo_out_I(3) when track_lo_out_OE(3) = '1' else 'Z';
    track_lo_out_OE(3) <= NOT track_lo(3);

    track_lo_out_I(4) <= '0';
    track_lo_out(4) <= track_lo_out_I(4) when track_lo_out_OE(4) = '1' else 'Z';
    track_lo_out_OE(4) <= NOT track_lo(4);

    track_lo_out_I(5) <= '0';
    track_lo_out(5) <= track_lo_out_I(5) when track_lo_out_OE(5) = '1' else 'Z';
    track_lo_out_OE(5) <= NOT track_lo(5);

    track_lo_out_I(6) <= '0';
    track_lo_out(6) <= track_lo_out_I(6) when track_lo_out_OE(6) = '1' else 'Z';
    track_lo_out_OE(6) <= NOT track_lo(6);

    FDCPE_turbo_rom_adr11: FDCPE port map (turbo_rom_adr(11),turbo_rom_adr_D(11),NOT phi2,'0','0');
    turbo_rom_adr_D(11) <= ((NOT turbo_rom_adr(11) AND
    	NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2)
    	OR (NOT data(4).PIN AND reset AND NOT data(6).PIN AND
    	turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2));

    FDCPE_turbo_rom_adr12: FDCPE port map (turbo_rom_adr(12),turbo_rom_adr_D(12),NOT phi2,'0','0');
    turbo_rom_adr_D(12) <= ((NOT turbo_rom_adr(12) AND
    	NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2)
    	OR (data(5).PIN AND reset AND
    	turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2));

    turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 <= ((NOT reset)
    	OR (adr(12) AND NOT floppy_mode(3) AND floppy_mode(2) AND
    	floppy_mode(0) AND NOT floppy_mode(1) AND NOT d7_ram_rom.PIN AND NOT adr(11)));

    turbo_speed_out <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND
    	NOT ms_speed_select AND $OpTx$FX_DC$551)
    	OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND
    	NOT floppy_mode(1) AND NOT riot_ready_inout.PIN)
    	OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(0) AND
    	NOT floppy_mode(1) AND turbo_speed_in));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ******************************  Device Pin Out *****************************

    Device : XC95144XL-10-TQ100

       --------------------------------------------------
      /100 98  96  94  92  90  88  86  84  82  80  78  76  \
     |   99  97  95  93  91  89  87  85  83  81  79  77    |
     | 1                                               75  |
     | 2                                               74  |
     | 3                                               73  |
     | 4                                               72  |
     | 5                                               71  |
     | 6                                               70  |
     | 7                                               69  |
     | 8                                               68  |
     | 9                                               67  |
     | 10                                              66  |
     | 11                                              65  |
     | 12                                              64  |
     | 13              XC95144XL-10-TQ100              63  |
     | 14                                              62  |
     | 15                                              61  |
     | 16                                              60  |
     | 17                                              59  |
     | 18                                              58  |
     | 19                                              57  |
     | 20                                              56  |
     | 21                                              55  |
     | 22                                              54  |
     | 23                                              53  |
     | 24                                              52  |
     | 25                                              51  |
     |   27  29  31  33  35  37  39  41  43  45  47  49    |
      \26  28  30  32  34  36  38  40  42  44  46  48  50  /
       --------------------------------------------------

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 ram_rom_adr<14>                  51 VCC
      2 ram_rom_adr<13>                  52 fdc_write_out
      3 turbo_speed_out                  53 archiver_a11
      4 turbo_speed_in                   54 fdc_write_in
      5 VCC                              55 riot_ready_inout
      6 adr<5>                           56 cfg_led
      7 ram_rom_adr<9>                   57 VCC
      8 adr<4>                           58 riot_ready_in
      9 adr<3>                           59 i2c_clk_pin
     10 adr<2>                           60 i2c_data_pin
     11 adr<1>                           61 cfg_sw2
     12 rom_ce                           62 GND
     13 adr<0>                           63 centronics_busy
     14 data<0>                          64 centronics_data
     15 data<2>                          65 centronics_strobe
     16 data<1>                          66 centronics_clk
     17 data<6>                          67 summer
     18 data<5>                          68 density_out<2>
     19 data<4>                          69 GND
     20 data<3>                          70 density_out<1>
     21 GND                              71 density_out<0>
     22 data<7>                          72 track_hi_out<6>
     23 rw                               73 cfg_enc_ok
     24 io_1050                          74 track_hi_out<5>
     25 adr<6>                           75 GND
     26 VCC                              76 track_hi_out<4>
     27 phi2                             77 track_hi_out<3>
     28 ram_rom_adr<11>                  78 track_hi_out<2>
     29 ram_rom_adr<8>                   79 track_hi_out<1>
     30 adr<7>                           80 cfg_sw1
     31 GND                              81 track_hi_out<0>
     32 adr<8>                           82 track_lo_out<6>
     33 adr<9>                           83 TDO
     34 ram_rom_adr<12>                  84 GND
     35 adr<10>                          85 track_lo_out<5>
     36 adr<11>                          86 track_lo_out<4>
     37 adr<13>                          87 track_lo_out<3>
     38 VCC                              88 VCC
     39 adr<14>                          89 track_lo_out<2>
     40 adr<15>                          90 track_lo_out<1>
     41 ram_rom_adr<10>                  91 track_lo_out<0>
     42 ram_ce                           92 cfg_enc_a
     43 adr<12>                          93 cfg_enc_b
     44 GND                              94 ram_rom_adr<18>
     45 TDI                              95 ram_rom_adr<17>
     46 d7_ram_rom                       96 ram_rom_adr<16>
     47 TMS                              97 ram_rom_adr<15>
     48 TCK                              98 VCC
     49 ram_rom_oe                       99 reset_in
     50 ram_rom_we                      100 GND

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             KPR  = Unused I/O with weak keeper (leave unconnected)
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc95144xl-10-TQ100
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : SLOW
    Power Mode                                  : LOW
    Ground on Unused IOs                        : OFF
    Set I/O Pin Termination                     : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Input Limit                                 : 35
    Pterm Limit                                 : 35