Timing Report

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Design Name MegaSpeedy
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Wed Nov 5 12:41:32 2014
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 41.900 ns.
Max. Clock Frequency (fSYSTEM) 23.866 MHz.
Limited by Cycle Time for phi2
Clock to Setup (tCYC) 41.900 ns.
Pad to Pad Delay (tPD) 90.200 ns.
Setup to Clock at the Pad (tSU) 38.400 ns.
Clock Pad to Output Pad Delay (tCO) 93.700 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_phi_we 20.0 20.0 1 0
TS_phi_oe 20.0 20.0 1 0
TS_phi2 1000.0 41.9 308 0


Constraint: TS_phi_we

Description: FROM:phi2:TO:ram_rom_we:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
phi2 to ram_rom_we 20.000 20.000 0.000


Constraint: TS_phi_oe

Description: FROM:phi2:TO:ram_rom_oe:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
phi2 to ram_rom_oe 20.000 20.000 0.000


Constraint: TS_phi2

Description: PERIOD:phi2:1000.000nS:HIGH:500.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
floppy_mode<0>.Q to centronics_clk.D 1000.000 41.900 958.100
floppy_mode<0>.Q to centronics_data.D 1000.000 41.900 958.100
floppy_mode<0>.Q to centronics_strobe.D 1000.000 41.900 958.100



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
phi2 23.866 Limited by Cycle Time for phi2

Setup/Hold Times for Clocks

Setup/Hold Times for Clock phi2
Source Pad Setup to clk (edge) Hold to clk (edge)
adr<0> 38.400 0.000
adr<10> 38.400 0.000
adr<11> 38.400 0.000
adr<12> 38.400 0.000
adr<13> 38.400 0.000
adr<14> 38.400 0.000
adr<15> 38.400 0.000
adr<1> 38.400 0.000
adr<2> 38.400 0.000
adr<3> 38.400 0.000
adr<4> 38.400 0.000
adr<5> 38.400 0.000
adr<6> 38.400 0.000
adr<7> 38.400 0.000
adr<8> 38.400 0.000
adr<9> 38.400 0.000
d7_ram_rom 25.200 0.000
data<0> 13.000 0.000
data<1> 13.000 0.000
data<2> 13.000 0.000
data<3> 13.000 0.000
data<4> 12.000 0.000
data<5> 12.000 0.000
data<6> 12.000 0.000
data<7> 12.000 0.000
reset_in 12.000 0.000
rw 26.200 0.000


Clock to Pad Timing

Clock phi2 to Pad
Destination Pad Clock (edge) to Pad
data<7> 93.700
d7_ram_rom 80.500
ram_rom_adr<16> 76.300
ram_rom_adr<17> 76.300
ram_rom_adr<18> 76.300
ram_ce 63.100
ram_rom_adr<14> 63.100
ram_rom_adr<11> 50.900
ram_rom_adr<12> 50.900
ram_rom_adr<13> 50.900
ram_rom_adr<10> 49.900
ram_rom_adr<15> 49.900
ram_rom_adr<8> 49.900
ram_rom_adr<9> 49.900
data<0> 40.900
data<1> 40.900
data<2> 40.900
data<3> 40.900
data<4> 40.900
data<5> 40.900
data<6> 40.900
fdc_write_out 36.700
io_1050 36.700
rom_ce 24.500
turbo_speed_out 23.500
i2c_clk_pin 14.500
i2c_data_pin 14.500
riot_ready_inout 14.500
centronics_clk 10.300
centronics_data 10.300
centronics_strobe 10.300
cfg_led 10.300
density<0> 10.300
density<1> 10.300
density<2> 10.300
summer 10.300
track_hi<0> 10.300
track_hi<1> 10.300
track_hi<2> 10.300
track_hi<3> 10.300
track_hi<4> 10.300
track_hi<5> 10.300
track_hi<6> 10.300
track_lo<0> 10.300
track_lo<1> 10.300
track_lo<2> 10.300
track_lo<3> 10.300
track_lo<4> 10.300
track_lo<5> 10.300
track_lo<6> 10.300


Clock to Setup Times for Clocks

Clock to Setup for clock phi2
Source Destination Delay
floppy_mode<0>.Q centronics_clk.D 41.900
floppy_mode<0>.Q centronics_data.D 41.900
floppy_mode<0>.Q centronics_strobe.D 41.900
floppy_mode<0>.Q cfg_led.D 41.900
floppy_mode<0>.Q floppy_mode<0>.D 41.900
floppy_mode<0>.Q floppy_mode<1>.D 41.900
floppy_mode<0>.Q floppy_mode<2>.D 41.900
floppy_mode<0>.Q floppy_mode<3>.D 41.900
floppy_mode<0>.Q ram_bank_0.D 41.900
floppy_mode<0>.Q ram_bank_1.D 41.900
floppy_mode<0>.Q ram_bank_2.D 41.900
floppy_mode<0>.Q ram_bank_3.D 41.900
floppy_mode<0>.Q ram_bank_4.D 41.900
floppy_mode<0>.Q rom_bank_c000_0.D 41.900
floppy_mode<0>.Q rom_bank_c000_1.D 41.900
floppy_mode<0>.Q rom_bank_c000_2.D 41.900
floppy_mode<0>.Q rom_bank_c000_3.D 41.900
floppy_mode<0>.Q rom_bank_c000_4.D 41.900
floppy_mode<0>.Q rom_bank_c000_5.D 41.900
floppy_mode<0>.Q rom_bank_c000_enable<0>.D 41.900
floppy_mode<0>.Q rom_base_bank_0.D 41.900
floppy_mode<0>.Q rom_base_bank_1.D 41.900
floppy_mode<0>.Q rom_base_bank_2.D 41.900
floppy_mode<0>.Q rom_base_bank_3.D 41.900
floppy_mode<0>.Q rom_base_bank_4.D 41.900
floppy_mode<0>.Q rom_base_bank_5.D 41.900
floppy_mode<0>.Q rom_base_bank_6.D 41.900
floppy_mode<0>.Q rom_source_is_ram.D 41.900
floppy_mode<0>.Q turbo_rom_adr<11>.D 41.900
floppy_mode<0>.Q turbo_rom_adr<12>.D 41.900
floppy_mode<1>.Q centronics_clk.D 41.900
floppy_mode<1>.Q centronics_data.D 41.900
floppy_mode<1>.Q centronics_strobe.D 41.900
floppy_mode<1>.Q cfg_led.D 41.900
floppy_mode<1>.Q floppy_mode<0>.D 41.900
floppy_mode<1>.Q floppy_mode<1>.D 41.900
floppy_mode<1>.Q floppy_mode<2>.D 41.900
floppy_mode<1>.Q floppy_mode<3>.D 41.900
floppy_mode<1>.Q ram_bank_0.D 41.900
floppy_mode<1>.Q ram_bank_1.D 41.900
floppy_mode<1>.Q ram_bank_2.D 41.900
floppy_mode<1>.Q ram_bank_3.D 41.900
floppy_mode<1>.Q ram_bank_4.D 41.900
floppy_mode<1>.Q rom_bank_c000_0.D 41.900
floppy_mode<1>.Q rom_bank_c000_1.D 41.900
floppy_mode<1>.Q rom_bank_c000_2.D 41.900
floppy_mode<1>.Q rom_bank_c000_3.D 41.900
floppy_mode<1>.Q rom_bank_c000_4.D 41.900
floppy_mode<1>.Q rom_bank_c000_5.D 41.900
floppy_mode<1>.Q rom_bank_c000_enable<0>.D 41.900
floppy_mode<1>.Q rom_base_bank_0.D 41.900
floppy_mode<1>.Q rom_base_bank_1.D 41.900
floppy_mode<1>.Q rom_base_bank_2.D 41.900
floppy_mode<1>.Q rom_base_bank_3.D 41.900
floppy_mode<1>.Q rom_base_bank_4.D 41.900
floppy_mode<1>.Q rom_base_bank_5.D 41.900
floppy_mode<1>.Q rom_base_bank_6.D 41.900
floppy_mode<1>.Q rom_source_is_ram.D 41.900
floppy_mode<1>.Q turbo_rom_adr<11>.D 41.900
floppy_mode<1>.Q turbo_rom_adr<12>.D 41.900
floppy_mode<2>.Q centronics_clk.D 41.900
floppy_mode<2>.Q centronics_data.D 41.900
floppy_mode<2>.Q centronics_strobe.D 41.900
floppy_mode<2>.Q cfg_led.D 41.900
floppy_mode<2>.Q floppy_mode<0>.D 41.900
floppy_mode<2>.Q floppy_mode<1>.D 41.900
floppy_mode<2>.Q floppy_mode<2>.D 41.900
floppy_mode<2>.Q floppy_mode<3>.D 41.900
floppy_mode<2>.Q ram_bank_0.D 41.900
floppy_mode<2>.Q ram_bank_1.D 41.900
floppy_mode<2>.Q ram_bank_2.D 41.900
floppy_mode<2>.Q ram_bank_3.D 41.900
floppy_mode<2>.Q ram_bank_4.D 41.900
floppy_mode<2>.Q rom_bank_c000_0.D 41.900
floppy_mode<2>.Q rom_bank_c000_1.D 41.900
floppy_mode<2>.Q rom_bank_c000_2.D 41.900
floppy_mode<2>.Q rom_bank_c000_3.D 41.900
floppy_mode<2>.Q rom_bank_c000_4.D 41.900
floppy_mode<2>.Q rom_bank_c000_5.D 41.900
floppy_mode<2>.Q rom_bank_c000_enable<0>.D 41.900
floppy_mode<2>.Q rom_base_bank_0.D 41.900
floppy_mode<2>.Q rom_base_bank_1.D 41.900
floppy_mode<2>.Q rom_base_bank_2.D 41.900
floppy_mode<2>.Q rom_base_bank_3.D 41.900
floppy_mode<2>.Q rom_base_bank_4.D 41.900
floppy_mode<2>.Q rom_base_bank_5.D 41.900
floppy_mode<2>.Q rom_base_bank_6.D 41.900
floppy_mode<2>.Q rom_source_is_ram.D 41.900
floppy_mode<2>.Q turbo_rom_adr<11>.D 41.900
floppy_mode<2>.Q turbo_rom_adr<12>.D 41.900
floppy_mode<3>.Q centronics_clk.D 41.900
floppy_mode<3>.Q centronics_data.D 41.900
floppy_mode<3>.Q centronics_strobe.D 41.900
floppy_mode<3>.Q cfg_led.D 41.900
floppy_mode<3>.Q floppy_mode<0>.D 41.900
floppy_mode<3>.Q floppy_mode<1>.D 41.900
floppy_mode<3>.Q floppy_mode<2>.D 41.900
floppy_mode<3>.Q floppy_mode<3>.D 41.900
floppy_mode<3>.Q ram_bank_0.D 41.900
floppy_mode<3>.Q ram_bank_1.D 41.900
floppy_mode<3>.Q ram_bank_2.D 41.900
floppy_mode<3>.Q ram_bank_3.D 41.900
floppy_mode<3>.Q ram_bank_4.D 41.900
floppy_mode<3>.Q rom_bank_c000_0.D 41.900
floppy_mode<3>.Q rom_bank_c000_1.D 41.900
floppy_mode<3>.Q rom_bank_c000_2.D 41.900
floppy_mode<3>.Q rom_bank_c000_3.D 41.900
floppy_mode<3>.Q rom_bank_c000_4.D 41.900
floppy_mode<3>.Q rom_bank_c000_5.D 41.900
floppy_mode<3>.Q rom_bank_c000_enable<0>.D 41.900
floppy_mode<3>.Q rom_base_bank_0.D 41.900
floppy_mode<3>.Q rom_base_bank_1.D 41.900
floppy_mode<3>.Q rom_base_bank_2.D 41.900
floppy_mode<3>.Q rom_base_bank_3.D 41.900
floppy_mode<3>.Q rom_base_bank_4.D 41.900
floppy_mode<3>.Q rom_base_bank_5.D 41.900
floppy_mode<3>.Q rom_base_bank_6.D 41.900
floppy_mode<3>.Q rom_source_is_ram.D 41.900
floppy_mode<3>.Q turbo_rom_adr<11>.D 41.900
floppy_mode<3>.Q turbo_rom_adr<12>.D 41.900
floppy_mode<0>.Q density<0>.D 29.700
floppy_mode<0>.Q density<1>.D 29.700
floppy_mode<0>.Q density<2>.D 29.700
floppy_mode<0>.Q i2c_clk.D 29.700
floppy_mode<0>.Q track_hi<0>.D 29.700
floppy_mode<0>.Q track_hi<1>.D 29.700
floppy_mode<0>.Q track_hi<2>.D 29.700
floppy_mode<0>.Q track_hi<3>.D 29.700
floppy_mode<0>.Q track_hi<4>.D 29.700
floppy_mode<0>.Q track_hi<5>.D 29.700
floppy_mode<0>.Q track_hi<6>.D 29.700
floppy_mode<0>.Q track_lo<0>.D 29.700
floppy_mode<0>.Q track_lo<1>.D 29.700
floppy_mode<0>.Q track_lo<2>.D 29.700
floppy_mode<0>.Q track_lo<3>.D 29.700
floppy_mode<0>.Q track_lo<4>.D 29.700
floppy_mode<0>.Q track_lo<5>.D 29.700
floppy_mode<0>.Q track_lo<6>.D 29.700
floppy_mode<1>.Q density<0>.D 29.700
floppy_mode<1>.Q density<1>.D 29.700
floppy_mode<1>.Q density<2>.D 29.700
floppy_mode<1>.Q i2c_clk.D 29.700
floppy_mode<1>.Q track_hi<0>.D 29.700
floppy_mode<1>.Q track_hi<1>.D 29.700
floppy_mode<1>.Q track_hi<2>.D 29.700
floppy_mode<1>.Q track_hi<3>.D 29.700
floppy_mode<1>.Q track_hi<4>.D 29.700
floppy_mode<1>.Q track_hi<5>.D 29.700
floppy_mode<1>.Q track_hi<6>.D 29.700
floppy_mode<1>.Q track_lo<0>.D 29.700
floppy_mode<1>.Q track_lo<1>.D 29.700
floppy_mode<1>.Q track_lo<2>.D 29.700
floppy_mode<1>.Q track_lo<3>.D 29.700
floppy_mode<1>.Q track_lo<4>.D 29.700
floppy_mode<1>.Q track_lo<5>.D 29.700
floppy_mode<1>.Q track_lo<6>.D 29.700
floppy_mode<2>.Q density<0>.D 29.700
floppy_mode<2>.Q density<1>.D 29.700
floppy_mode<2>.Q density<2>.D 29.700
floppy_mode<2>.Q i2c_clk.D 29.700
floppy_mode<2>.Q track_hi<0>.D 29.700
floppy_mode<2>.Q track_hi<1>.D 29.700
floppy_mode<2>.Q track_hi<2>.D 29.700
floppy_mode<2>.Q track_hi<3>.D 29.700
floppy_mode<2>.Q track_hi<4>.D 29.700
floppy_mode<2>.Q track_hi<5>.D 29.700
floppy_mode<2>.Q track_hi<6>.D 29.700
floppy_mode<2>.Q track_lo<0>.D 29.700
floppy_mode<2>.Q track_lo<1>.D 29.700
floppy_mode<2>.Q track_lo<2>.D 29.700
floppy_mode<2>.Q track_lo<3>.D 29.700
floppy_mode<2>.Q track_lo<4>.D 29.700
floppy_mode<2>.Q track_lo<5>.D 29.700
floppy_mode<2>.Q track_lo<6>.D 29.700
floppy_mode<3>.Q density<0>.D 29.700
floppy_mode<3>.Q density<1>.D 29.700
floppy_mode<3>.Q density<2>.D 29.700
floppy_mode<3>.Q i2c_clk.D 29.700
floppy_mode<3>.Q track_hi<0>.D 29.700
floppy_mode<3>.Q track_hi<1>.D 29.700
floppy_mode<3>.Q track_hi<2>.D 29.700
floppy_mode<3>.Q track_hi<3>.D 29.700
floppy_mode<3>.Q track_hi<4>.D 29.700
floppy_mode<3>.Q track_hi<5>.D 29.700
floppy_mode<3>.Q track_hi<6>.D 29.700
floppy_mode<3>.Q track_lo<0>.D 29.700
floppy_mode<3>.Q track_lo<1>.D 29.700
floppy_mode<3>.Q track_lo<2>.D 29.700
floppy_mode<3>.Q track_lo<3>.D 29.700
floppy_mode<3>.Q track_lo<4>.D 29.700
floppy_mode<3>.Q track_lo<5>.D 29.700
floppy_mode<3>.Q track_lo<6>.D 29.700
floppy_mode<0>.Q happy_a12.D 28.700
floppy_mode<0>.Q i2c_data.D 28.700
floppy_mode<0>.Q ram_bank_5.D 28.700
floppy_mode<1>.Q happy_a12.D 28.700
floppy_mode<1>.Q i2c_data.D 28.700
floppy_mode<1>.Q ram_bank_5.D 28.700
floppy_mode<2>.Q happy_a12.D 28.700
floppy_mode<2>.Q i2c_data.D 28.700
floppy_mode<2>.Q ram_bank_5.D 28.700
floppy_mode<3>.Q happy_a12.D 28.700
floppy_mode<3>.Q i2c_data.D 28.700
floppy_mode<3>.Q ram_bank_5.D 28.700
reset.Q centronics_clk.D 28.700
reset.Q centronics_data.D 28.700
reset.Q centronics_strobe.D 28.700
reset.Q floppy_mode<0>.D 28.700
reset.Q floppy_mode<1>.D 28.700
reset.Q floppy_mode<2>.D 28.700
reset.Q floppy_mode<3>.D 28.700
reset.Q happy_a12.D 28.700
reset.Q ram_bank_0.D 28.700
reset.Q ram_bank_1.D 28.700
reset.Q ram_bank_2.D 28.700
reset.Q ram_bank_3.D 28.700
reset.Q ram_bank_4.D 28.700
reset.Q rom_bank_c000_0.D 28.700
reset.Q rom_bank_c000_1.D 28.700
reset.Q rom_bank_c000_2.D 28.700
reset.Q rom_bank_c000_3.D 28.700
reset.Q rom_bank_c000_4.D 28.700
reset.Q rom_bank_c000_5.D 28.700
reset.Q rom_bank_c000_enable<0>.D 28.700
reset.Q rom_base_bank_0.D 28.700
reset.Q rom_base_bank_1.D 28.700
reset.Q rom_base_bank_2.D 28.700
reset.Q rom_base_bank_3.D 28.700
reset.Q rom_base_bank_4.D 28.700
reset.Q rom_base_bank_5.D 28.700
reset.Q rom_base_bank_6.D 28.700
reset.Q rom_source_is_ram.D 28.700
reset.Q turbo_rom_adr<11>.D 28.700
reset.Q turbo_rom_adr<12>.D 28.700
i2c_clk.Q i2c_clk.D 16.500
reset.Q i2c_clk.D 16.500
centronics_clk.Q centronics_clk.D 15.500
centronics_data.Q centronics_data.D 15.500
centronics_strobe.Q centronics_strobe.D 15.500
cfg_led.Q cfg_led.D 15.500
density<0>.Q density<0>.D 15.500
density<1>.Q density<1>.D 15.500
density<2>.Q density<2>.D 15.500
floppy_mode<0>.Q summer.D 15.500
floppy_mode<1>.Q summer.D 15.500
floppy_mode<2>.Q summer.D 15.500
floppy_mode<3>.Q summer.D 15.500
happy_a12.Q happy_a12.D 15.500
i2c_data.Q i2c_data.D 15.500
ram_bank_0.Q ram_bank_0.D 15.500
ram_bank_1.Q ram_bank_1.D 15.500
ram_bank_2.Q ram_bank_2.D 15.500
ram_bank_3.Q ram_bank_3.D 15.500
ram_bank_4.Q ram_bank_4.D 15.500
ram_bank_5.Q ram_bank_5.D 15.500
reset.Q cfg_led.D 15.500
reset.Q density<0>.D 15.500
reset.Q density<1>.D 15.500
reset.Q density<2>.D 15.500
reset.Q i2c_data.D 15.500
reset.Q ram_bank_5.D 15.500
reset.Q summer.D 15.500
reset.Q track_hi<0>.D 15.500
reset.Q track_hi<1>.D 15.500
reset.Q track_hi<2>.D 15.500
reset.Q track_hi<3>.D 15.500
reset.Q track_hi<4>.D 15.500
reset.Q track_hi<5>.D 15.500
reset.Q track_hi<6>.D 15.500
reset.Q track_lo<0>.D 15.500
reset.Q track_lo<1>.D 15.500
reset.Q track_lo<2>.D 15.500
reset.Q track_lo<3>.D 15.500
reset.Q track_lo<4>.D 15.500
reset.Q track_lo<5>.D 15.500
reset.Q track_lo<6>.D 15.500
reset_sync.Q reset.D 15.500
rom_bank_c000_0.Q rom_bank_c000_0.D 15.500
rom_bank_c000_1.Q rom_bank_c000_1.D 15.500
rom_bank_c000_2.Q rom_bank_c000_2.D 15.500
rom_bank_c000_3.Q rom_bank_c000_3.D 15.500
rom_bank_c000_4.Q rom_bank_c000_4.D 15.500
rom_bank_c000_5.Q rom_bank_c000_5.D 15.500
rom_bank_c000_enable<0>.Q rom_bank_c000_enable<0>.D 15.500
rom_base_bank_0.Q rom_base_bank_0.D 15.500
rom_base_bank_1.Q rom_base_bank_1.D 15.500
rom_base_bank_2.Q rom_base_bank_2.D 15.500
rom_base_bank_3.Q rom_base_bank_3.D 15.500
rom_base_bank_4.Q rom_base_bank_4.D 15.500
rom_base_bank_5.Q rom_base_bank_5.D 15.500
rom_base_bank_6.Q rom_base_bank_6.D 15.500
rom_source_is_ram.Q rom_source_is_ram.D 15.500
track_hi<0>.Q track_hi<0>.D 15.500
track_hi<1>.Q track_hi<1>.D 15.500
track_hi<2>.Q track_hi<2>.D 15.500
track_hi<3>.Q track_hi<3>.D 15.500
track_hi<4>.Q track_hi<4>.D 15.500
track_hi<5>.Q track_hi<5>.D 15.500
track_hi<6>.Q track_hi<6>.D 15.500
track_lo<0>.Q track_lo<0>.D 15.500
track_lo<1>.Q track_lo<1>.D 15.500
track_lo<2>.Q track_lo<2>.D 15.500
track_lo<3>.Q track_lo<3>.D 15.500
track_lo<4>.Q track_lo<4>.D 15.500
track_lo<5>.Q track_lo<5>.D 15.500
track_lo<6>.Q track_lo<6>.D 15.500
turbo_rom_adr<11>.Q turbo_rom_adr<11>.D 15.500
turbo_rom_adr<12>.Q turbo_rom_adr<12>.D 15.500


Pad to Pad List

Source Pad Destination Pad Delay
adr<12> data<7> 90.200
adr<13> data<7> 90.200
adr<14> data<7> 90.200
adr<15> data<7> 90.200
adr<10> data<7> 77.000
adr<12> d7_ram_rom 77.000
adr<13> d7_ram_rom 77.000
adr<14> d7_ram_rom 77.000
adr<15> d7_ram_rom 77.000
adr<7> data<7> 77.000
adr<9> data<7> 77.000
adr<12> ram_rom_adr<16> 72.800
adr<12> ram_rom_adr<17> 72.800
adr<12> ram_rom_adr<18> 72.800
adr<13> ram_rom_adr<16> 72.800
adr<13> ram_rom_adr<17> 72.800
adr<13> ram_rom_adr<18> 72.800
adr<14> ram_rom_adr<16> 72.800
adr<14> ram_rom_adr<17> 72.800
adr<14> ram_rom_adr<18> 72.800
adr<15> ram_rom_adr<16> 72.800
adr<15> ram_rom_adr<17> 72.800
adr<15> ram_rom_adr<18> 72.800
adr<11> data<7> 64.800
adr<10> d7_ram_rom 63.800
adr<7> d7_ram_rom 63.800
adr<9> d7_ram_rom 63.800
rw data<7> 63.800
adr<10> ram_rom_adr<16> 59.600
adr<10> ram_rom_adr<17> 59.600
adr<10> ram_rom_adr<18> 59.600
adr<12> ram_ce 59.600
adr<12> ram_rom_adr<14> 59.600
adr<13> ram_ce 59.600
adr<13> ram_rom_adr<14> 59.600
adr<14> ram_ce 59.600
adr<14> ram_rom_adr<14> 59.600
adr<15> ram_ce 59.600
adr<15> ram_rom_adr<14> 59.600
adr<7> ram_rom_adr<16> 59.600
adr<7> ram_rom_adr<17> 59.600
adr<7> ram_rom_adr<18> 59.600
adr<9> ram_rom_adr<16> 59.600
adr<9> ram_rom_adr<17> 59.600
adr<9> ram_rom_adr<18> 59.600
adr<11> d7_ram_rom 51.600
adr<0> data<0> 50.600
adr<0> data<1> 50.600
adr<0> data<2> 50.600
adr<0> data<3> 50.600
adr<0> data<4> 50.600
adr<0> data<5> 50.600
adr<0> data<6> 50.600
adr<0> data<7> 50.600
adr<10> data<0> 50.600
adr<10> data<1> 50.600
adr<10> data<2> 50.600
adr<10> data<3> 50.600
adr<10> data<4> 50.600
adr<10> data<5> 50.600
adr<10> data<6> 50.600
adr<11> data<0> 50.600
adr<11> data<1> 50.600
adr<11> data<2> 50.600
adr<11> data<3> 50.600
adr<11> data<4> 50.600
adr<11> data<5> 50.600
adr<11> data<6> 50.600
adr<12> data<0> 50.600
adr<12> data<1> 50.600
adr<12> data<2> 50.600
adr<12> data<3> 50.600
adr<12> data<4> 50.600
adr<12> data<5> 50.600
adr<12> data<6> 50.600
adr<13> data<0> 50.600
adr<13> data<1> 50.600
adr<13> data<2> 50.600
adr<13> data<3> 50.600
adr<13> data<4> 50.600
adr<13> data<5> 50.600
adr<13> data<6> 50.600
adr<14> data<0> 50.600
adr<14> data<1> 50.600
adr<14> data<2> 50.600
adr<14> data<3> 50.600
adr<14> data<4> 50.600
adr<14> data<5> 50.600
adr<14> data<6> 50.600
adr<15> data<0> 50.600
adr<15> data<1> 50.600
adr<15> data<2> 50.600
adr<15> data<3> 50.600
adr<15> data<4> 50.600
adr<15> data<5> 50.600
adr<15> data<6> 50.600
adr<1> data<0> 50.600
adr<1> data<1> 50.600
adr<1> data<2> 50.600
adr<1> data<3> 50.600
adr<1> data<4> 50.600
adr<1> data<5> 50.600
adr<1> data<6> 50.600
adr<1> data<7> 50.600
adr<2> data<0> 50.600
adr<2> data<1> 50.600
adr<2> data<2> 50.600
adr<2> data<3> 50.600
adr<2> data<4> 50.600
adr<2> data<5> 50.600
adr<2> data<6> 50.600
adr<2> data<7> 50.600
adr<3> data<0> 50.600
adr<3> data<1> 50.600
adr<3> data<2> 50.600
adr<3> data<3> 50.600
adr<3> data<4> 50.600
adr<3> data<5> 50.600
adr<3> data<6> 50.600
adr<3> data<7> 50.600
adr<4> data<0> 50.600
adr<4> data<1> 50.600
adr<4> data<2> 50.600
adr<4> data<3> 50.600
adr<4> data<4> 50.600
adr<4> data<5> 50.600
adr<4> data<6> 50.600
adr<4> data<7> 50.600
adr<5> data<0> 50.600
adr<5> data<1> 50.600
adr<5> data<2> 50.600
adr<5> data<3> 50.600
adr<5> data<4> 50.600
adr<5> data<5> 50.600
adr<5> data<6> 50.600
adr<5> data<7> 50.600
adr<6> data<0> 50.600
adr<6> data<1> 50.600
adr<6> data<2> 50.600
adr<6> data<3> 50.600
adr<6> data<4> 50.600
adr<6> data<5> 50.600
adr<6> data<6> 50.600
adr<6> data<7> 50.600
adr<7> data<0> 50.600
adr<7> data<1> 50.600
adr<7> data<2> 50.600
adr<7> data<3> 50.600
adr<7> data<4> 50.600
adr<7> data<5> 50.600
adr<7> data<6> 50.600
adr<8> data<0> 50.600
adr<8> data<1> 50.600
adr<8> data<2> 50.600
adr<8> data<3> 50.600
adr<8> data<4> 50.600
adr<8> data<5> 50.600
adr<8> data<6> 50.600
adr<8> data<7> 50.600
adr<9> data<0> 50.600
adr<9> data<1> 50.600
adr<9> data<2> 50.600
adr<9> data<3> 50.600
adr<9> data<4> 50.600
adr<9> data<5> 50.600
adr<9> data<6> 50.600
rw d7_ram_rom 50.600
adr<11> ram_rom_adr<16> 47.400
adr<11> ram_rom_adr<17> 47.400
adr<11> ram_rom_adr<18> 47.400
adr<12> ram_rom_adr<11> 47.400
adr<12> ram_rom_adr<12> 47.400
adr<12> ram_rom_adr<13> 47.400
adr<13> ram_rom_adr<11> 47.400
adr<13> ram_rom_adr<12> 47.400
adr<13> ram_rom_adr<13> 47.400
adr<14> ram_rom_adr<11> 47.400
adr<14> ram_rom_adr<12> 47.400
adr<14> ram_rom_adr<13> 47.400
adr<15> ram_rom_adr<11> 47.400
adr<15> ram_rom_adr<12> 47.400
adr<15> ram_rom_adr<13> 47.400
adr<10> ram_ce 46.400
adr<10> ram_rom_adr<14> 46.400
adr<12> ram_rom_adr<10> 46.400
adr<12> ram_rom_adr<15> 46.400
adr<12> ram_rom_adr<8> 46.400
adr<12> ram_rom_adr<9> 46.400
adr<13> ram_rom_adr<10> 46.400
adr<13> ram_rom_adr<15> 46.400
adr<13> ram_rom_adr<8> 46.400
adr<13> ram_rom_adr<9> 46.400
adr<14> ram_rom_adr<10> 46.400
adr<14> ram_rom_adr<15> 46.400
adr<14> ram_rom_adr<8> 46.400
adr<14> ram_rom_adr<9> 46.400
adr<15> ram_rom_adr<10> 46.400
adr<15> ram_rom_adr<15> 46.400
adr<15> ram_rom_adr<8> 46.400
adr<15> ram_rom_adr<9> 46.400
adr<7> ram_ce 46.400
adr<7> ram_rom_adr<14> 46.400
adr<9> ram_ce 46.400
adr<9> ram_rom_adr<14> 46.400
rw ram_rom_adr<16> 46.400
rw ram_rom_adr<17> 46.400
rw ram_rom_adr<18> 46.400
adr<10> ram_rom_adr<11> 34.200
adr<10> ram_rom_adr<12> 34.200
adr<10> ram_rom_adr<13> 34.200
adr<10> ram_rom_adr<15> 34.200
adr<11> ram_ce 34.200
adr<11> ram_rom_adr<14> 34.200
adr<11> ram_rom_adr<15> 34.200
adr<7> ram_rom_adr<11> 34.200
adr<7> ram_rom_adr<12> 34.200
adr<7> ram_rom_adr<13> 34.200
adr<7> ram_rom_adr<15> 34.200
adr<9> ram_rom_adr<11> 34.200
adr<9> ram_rom_adr<12> 34.200
adr<9> ram_rom_adr<13> 34.200
rw ram_rom_adr<15> 34.200
adr<10> ram_rom_adr<10> 33.200
adr<10> ram_rom_adr<8> 33.200
adr<10> ram_rom_adr<9> 33.200
adr<11> ram_rom_adr<13> 33.200
adr<12> io_1050 33.200
adr<13> io_1050 33.200
adr<14> io_1050 33.200
adr<15> io_1050 33.200
adr<7> ram_rom_adr<10> 33.200
adr<7> ram_rom_adr<8> 33.200
adr<7> ram_rom_adr<9> 33.200
adr<9> ram_rom_adr<10> 33.200
adr<9> ram_rom_adr<15> 33.200
adr<9> ram_rom_adr<8> 33.200
adr<9> ram_rom_adr<9> 33.200
rw ram_ce 33.200
rw ram_rom_adr<14> 33.200
phi2 data<0> 24.200
phi2 data<1> 24.200
phi2 data<2> 24.200
phi2 data<3> 24.200
phi2 data<4> 24.200
phi2 data<5> 24.200
phi2 data<6> 24.200
phi2 data<7> 24.200
rw data<0> 24.200
rw data<1> 24.200
rw data<2> 24.200
rw data<3> 24.200
rw data<4> 24.200
rw data<5> 24.200
rw data<6> 24.200
adr<10> io_1050 21.000
adr<11> io_1050 21.000
adr<11> ram_rom_adr<12> 21.000
adr<13> rom_ce 21.000
adr<14> rom_ce 21.000
adr<15> rom_ce 21.000
adr<7> io_1050 21.000
archiver_a11 ram_rom_adr<11> 21.000
centronics_busy data<7> 21.000
d7_ram_rom data<7> 21.000
i2c_data_pin data<7> 21.000
rw ram_rom_adr<11> 21.000
rw ram_rom_adr<13> 21.000
rw rom_ce 21.000
adr<11> ram_rom_adr<11> 20.000
adr<11> rom_ce 20.000
adr<12> rom_ce 20.000
adr<8> ram_rom_adr<8> 20.000
adr<9> io_1050 20.000
archiver_a11 fdc_write_out 20.000
cfg_enc_a data<0> 20.000
cfg_enc_b data<1> 20.000
cfg_enc_ok data<2> 20.000
cfg_sw1 data<3> 20.000
cfg_sw2 data<4> 20.000
fdc_write_in fdc_write_out 20.000
phi2 ram_rom_oe 20.000
phi2 ram_rom_we 20.000
riot_ready_in riot_ready_inout 20.000
riot_ready_inout turbo_speed_out 20.000
rw ram_rom_adr<12> 20.000
rw ram_rom_oe 20.000
rw ram_rom_we 20.000
turbo_speed_in turbo_speed_out 20.000
data<7> d7_ram_rom 16.500
phi2 d7_ram_rom 11.000


Number of paths analyzed: 310
Number of Timing errors: 0
Analysis Completed: Wed Nov 5 12:41:32 2014